12004 MAPLD: 153Brej Early output logic and Anti-Tokens Charlie Brej APT Group Manchester University

22004 MAPLD: 153Brej Overview  Synchronous Problems  Asynchronous Logic  Why?  How?  Solutions  Early Output  Anti-Tokens

32004 MAPLD: 153Brej Problems: Communication  Communication horizon  “For a 60 nanometer process a signal can reach only 5% of the die’s length in a clock cycle” [D. Matzke,1997]  Clock distributed using wave pipelining

42004 MAPLD: 153Brej Problems: Performance Cycle time Unbalanced Stages Clock Skew/Jitter Transistor Variability Signal Integrity Worst – Average case performance Real Computation Clock overheads Timing Assumption overheads

52004 MAPLD: 153Brej Clock! What is it good for?  No arguing with the clock  9am - 5pm. No excuses!

62004 MAPLD: 153Brej Bundled-Data  When you finish, do the next task  Flexitime Request + Delay Acknowledge

72004 MAPLD: 153Brej How do you know when you are finished?  Synchronous:  Estimate  Global timing reference  Asynchronous (bundled-data)  Estimate  Local delay elements  Asynchronous (delay-insensitive)  When the data arrives  Intrinsic

82004 MAPLD: 153Brej Becoming Delay Insensitive  Dual-Rail  Two wires  00 – NULL  01 – Zero  10 – One  (11 – Not used)  Four Phase handshake  Return to zero R1 Ack R0

92004 MAPLD: 153Brej Early Output Logic  Dual-Rail interfaces  Output generated as early as possible  Two Early output cases  If either input is ‘0’ then the output is ‘0’

MAPLD: 153Brej Bit level pipelining  Forward completed parts of the result  Pace work  Don’t stall parts unless you have to

MAPLD: 153Brej Bit level pipelining  Forward completed parts of the result  Pace work  Don’t stall parts unless you have to

MAPLD: 153Brej Bit level pipelining  Forward completed parts of the result  Pace work  Don’t stall parts unless you have to

MAPLD: 153Brej Early Output cases

MAPLD: 153Brej Validity  Unnecessary late inputs  Must be acknowledged  Must wait until they arrive  Validity signal  Latch generated  Ready to be acknowledged  Result before all inputs present  Acknowledge after all inputs present

MAPLD: 153Brej Synchronisation Hurts  No need to wait before generating result  Need to wait for input in order to acknowledge it  Unnecessary stall

MAPLD: 153Brej Anti-Tokens  Unnecessary late inputs  Stall the entire stage  Proactive approach  Send a ‘cancel’ signal backward to the source  Acknowledge before data arrives  Anti-Token latches  Assert validity early

MAPLD: 153Brej Anti-token generation 0 1 C

MAPLD: 153Brej Anti-token generation 0 A 1 C

MAPLD: 153Brej Anti-token Propagation 1 C A

MAPLD: 153Brej Anti-token Propagation 1 C A A

MAPLD: 153Brej Anti-token Token collisions 11 AA 11 AA ? A ? 1

MAPLD: 153Brej Anti-token Token collisions 11 A 11 AA 1 A1 1 1

MAPLD: 153Brej Remove Unnecessary computation Cycle time Unbalanced Stages Clock Skew/Jitter Transistor Variability Signal Integrity Worst – Average case performance Real Computation Clock overheads Timing Assumption overheads Unnecessary Computation/Delays

MAPLD: 153Brej Summary  Asynchronous  Delay Insensitive  Safe  No timing assumptions  Average case performance  Remove unnecessary computation  Anti-tokens without mutual exclusion units