Mask Registration and its Modeling Implications David Schwan - Engineering Manager - RFMD a) The IC fabrication process uses Photomasks. b) Masks are aligned either to a “Zero Layer” or to the previous layer. c) Alignment is subject to variation in X and Y directions, and will be obey normal statistical distributions d) These variations can cause mismatches in analog circuits, and timing errors in digital circuits. e) Mismatch due to misalignment is not found by running Monte Carlo simulations. f) Conventional RC extraction assumes perfect mask alignment. g) Misalignment creates systemic mismatches. h) Analog circuits will function, but yield (measurement of critical specs) will follow normal distribution. i) Digital circuits may experience timing errors. As AD and PD get smaller, then delay becomes smaller. Similarly as AD and PD get larger, then delay becomes greater. j) Accounting for the three sigma misalignment, in 0.35u CMOS, the delay of the gate can be effected by ±8%, for well designed cells, and ±30% for poorly designed cells.

Mirrored Devices are not Matched Poly Alignment Left Drain -> AD, PD are larger Right Drain -> AD, PD are smaller Left Source -> AS, PS are smaller Right Source -> AS, PS are larger

Suggestions for Implementation a)Circuit designers are in need of a way to predict whether their circuit has sensitivities to mask registration. b)Building sensitive information (alignment data) into simulation model allows user to leverage this information, and gain insight into their circuit. c)Value in microns (or nm) is typically not released, this is considered proprietary information d)Structures can be built to measure amount of misalignment; requires special knowledge on the part of the designer. e)Add modeling for this to the statistical model. Any change to AD/PD/NRD need to be mirrored by an opposite change to AS/PS/NRS. Example: AD=AS=1um 2 PD=PS=3um With example shift (0.1um): AD=0.8um2 AS=1.2um2 PD=2.8um PS=3.2um NRD and NRS need to change accordingly.