1. A 333MHz DRAM with Floating Body Cell (FBC) VLSI Systems I Fall 2007 Hamid Abbasalizadeh

2. Introduction to the Floating Body Cell (FBC) [1] Berkeley Started the FBC and then Toshiba continued. Intel introduced more advanced one using (two gates) front and back. The idea is to eliminate the capacitor from conventional DRAM; therefore, it is more denser faster and easier to make, but still slower than SRAMs. Floating Body (FB) part retains the charge based on the thickness of the Bottom Oxide (BOX), and the BG voltage difference. FBC cells do not need to be refreshed every cycle. They only need to be refilled with a few holes for logic “1” that is way faster than refreshing time of the conventional DRAMs. [1] http://www.theinquirer.net/default.aspx?article=36285

3. Paper’s Objectives [2] To show by Monte Carlo simulation that FBC DRAM’s read cycle speed can go up to 333MHz. This improvement is done by introducing a symmetrical sense amplifier with an improved current mirror ratio. Improvement of the sense amplifier means reducing the t PREAMP. FBC cell only need to be restored for logic ‘1’, and it only needs to be refilled with a few holes lost by charge pumping phenomenon every time its word line is activated.

4. Speed Improvement of the Sense Amplifier by Making Current Mirror Symmetrical [2] Conventional Sense AmplifierIntroduced Symmetrical Sense Amplifier

5. Pre-amp’s Gain and Speed & Speed Comparison Between FBC DRAMs & Conventional DRAMs [2] Making ratio of M2/M1 larger than 1, in other words, increasing the gain of the pre-amplification reduces the t PREAMP, unless, there is a process variation. In case of process variation, increasing the gain will make the pre- amp unstable. Read cycle time (t RC ) of the FBC DRAMs looks very promising compare to conventional DRAMs Also FBC (3) is denser than a conventional 165nm DRAM [2] Hatsuda, K.; Fujita, K.; Ohsawa, T. ‘A 333MHz random cycle DRAM using the floating body cell’ Custom Integrated Circuits Conference, Proceedings of the IEEE, Sept. 2005