COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE LECTURE # 10 BY MUHAMMAD JAFER 1

CENTERAL PROCESSING UNIT Register Set Athematic Logic Unit Control Unit Data path 2

INSTRUCTION CYCLE Instruction Register 3

DATA PATH Capable of performing certain operation on data Athematic Logic Unit External Busses & Internal Busses Both can have different design 4

ONE-BUS ORGANIZATION Single Bus One instruction fetching per CPU cycle Simple & Cheapest Slow 5

TWO-BUS ORGANIZATION two Bus Two instruction fetching per CPU cycle In-bus & Out-bus design 6

THREE-BUS ORGANIZATION Three Bus Two In-bus & one Out-bus design More busses will have data transfer faster More complex hardware design Expensive 7

INSTRUCTION CYCLE EXAMPLES MOV AL,5 ADD AL,[003] 8

COMPLEX INSTRUCTION CYCLE 9

INTERRUPTS Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program e.g. overflow, division by zero Timer Generated by internal processor timer Used in pre-emptive multi-tasking I/O from I/O controller Hardware failure e.g. memory parity error 10

IF INTERRUPTS Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program 11

IF INTERRUPTS 12

IF INTERRUPTS Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program 13

PROGRAM TIMING SHORT I/O WAIT 14

PROGRAM TIMING LONG I/O WAIT 15

CONTROL UNIT Part of CPU Management of Computer Resources Control and Timing Signals Directs Flow of Data CU Types Mircoprogrammed Hardwire 16

MICROPROGRAMMED Memory Units storing Control Signals Inaccessible Memory Units in RAM or ROM Control Word is microinstruction Microinstruction = 1/More Microoperations Sequence of microinstructions are microprograms 17

HARDWIRED Fixed Logical Instructions Far more faster Not cheaper & Complex 18

CHAPTER REVIEW Fundamentals of Computer Organization and Architecture by Mostafa Abd-Al-Barr & Hesham AlRewini Chapter # 5 CPU Basics Register Set Datapath CPU Instruction Cycle Control Unit 19