A Negotiated Congestion based Router for Simultaneous Escape Routing Q.Ma, T.Yan and Martin D.F. Wong Department of Electrical and Computer Engineering.

Slides:



Advertisements
Similar presentations
Optimal Bus Sequencing for Escape Routing in Dense PCBs H.Kong, T.Yan, M.D.F.Wong and M.M.Ozdal Department of ECE, University of Illinois at U-C ICCAD.
Advertisements

Constraint Driven I/O Planning and Placement for Chip-package Co-design Jinjun Xiong, Yiuchung Wong, Egino Sarto, Lei He University of California, Los.
A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.
Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.
Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
Shuai Li and Cheng-Kok Koh School of Electrical and Computer Engineering, Purdue University West Lafayette, IN, Mixed Integer Programming Models.
Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.
EXPLORING HIGH THROUGHPUT COMPUTING PARADIGM FOR GLOBAL ROUTING Yiding Han, Dean Michael Ancajas, Koushik Chakraborty, and Sanghamitra Roy Electrical and.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
An ILP-based Automatic Bus Planner for Dense PCBs P. C. Wu, Q. Ma and M. D. F. Wong Department of Electrical and Computer Engineering, University of Illinois.
MCFRoute: A Detailed Router Based on Multi- Commodity Flow Method Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li.
38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.
ECE Routing 1 ECE 665 Spring 2004 ECE 665 Spring 2004 Computer Algorithms with Applications to VLSI CAD Channel Routing Global Routing.
3.3 Multi-Layer V i+1 H i Channel Routing Presented by Md. Shaifur Rahman Student #
A Resource-level Parallel Approach for Global-routing-based Routing Congestion Estimation and a Method to Quantify Estimation Accuracy Wen-Hao Liu, Zhen-Yu.
Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost W. Liu, T. Chien and T. Wang Department of CS, NTHU,
Constrained Pattern Assignment for Standard Cell Based Triple Patterning Lithography H. Tian, Y. Du, H. Zhang, Z. Xiao, M. D.F. Wong Department of ECE,
7/13/ EE4271 VLSI Design VLSI Routing. 2 7/13/2015 Routing Problem Routing to reduce the area.
Routing 2 Outline –Maze Routing –Line Probe Routing –Channel Routing Goal –Understand maze routing –Understand line probe routing.
CDCTree: Novel Obstacle-Avoiding Routing Tree Construction based on Current Driven Circuit Model Speaker: Lei He.
General Routing Overview and Channel Routing
Introduction to Routing. The Routing Problem Apply after placement Input: –Netlist –Timing budget for, typically, critical nets –Locations of blocks and.
MGR: Multi-Level Global Router Yue Xu and Chris Chu Department of Electrical and Computer Engineering Iowa State University ICCAD
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.
Authors: Jia-Wei Fang,Chin-Hsiung Hsu,and Yao-Wen Chang DAC 2007 speaker: sheng yi An Integer Linear Programming Based Routing Algorithm for Flip-Chip.
Escape Routing For Dense Pin Clusters In Integrated Circuits Mustafa Ozdal, Design Automation Conference, 2007 Mustafa Ozdal, IEEE Trans. on CAD, 2009.
CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles Y. Kohira and A. Takahashi School of Computer Science.
Global Routing.
FPGA Switch Block Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.
Solving Hard Instances of FPGA Routing with a Congestion-Optimal Restrained-Norm Path Search Space Keith So School of Computer Science and Engineering.
1 Global Routing Method for 2-Layer Ball Grid Array Packages Yukiko Kubo*, Atsushi Takahashi** * The University of Kitakyushu ** Tokyo Institute of Technology.
Wen-Hao Liu 1, Yih-Lang Li 1, and Kai-Yuan Chao 2 1 Department of Computer Science, National Chiao-Tung University, Hsin-Chu, Taiwan 2 Intel Architecture.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig 1 EECS 527 Paper Presentation High-Performance.
Archer: A History-Driven Global Routing Algorithm Mustafa Ozdal Intel Corporation Martin D. F. Wong Univ. of Illinois at Urbana-Champaign Mustafa Ozdal.
BSG-Route: A Length-Matching Router for General Topology T. Yan and M. D. F. Wong University of Illinois at Urbana-Champaign ICCAD 2008.
New Modeling Techniques for the Global Routing Problem Anthony Vannelli Department of Electrical and Computer Engineering University of Waterloo Waterloo,
1 CS612 Algorithms for Electronic Design Automation CS 612 – Lecture 8 Lecture 8 Network Flow Based Modeling Mustafa Ozdal Computer Engineering Department,
Thermal-aware Steiner Routing for 3D Stacked ICs M. Pathak and S.K. Lim Georgia Institute of Technology ICCAD 07.
Bus-Pin-Aware Bus-Driven Floorplanning B. Wu and T. Ho Department of Computer Science and Information Engineering NCKU GLSVLSI 2010.
A Routing Approach to Reduce Glitches in Low Power FPGAs Quang Dinh, Deming Chen, Martin D. F. Wong Department of Electrical and Computer Engineering University.
AUTOMATIC BUS PLANNER FOR DENSE PCBS Hui Kong, Tan Yan and Martin D.F. Wong Department of Electrical and Computer Engineering, University of Illinois at.
Ping-Hung Yuh, Chia-Lin Yang, and Yao-Wen Chang
IO CONNECTION ASSIGNMENT AND RDL ROUTING FOR FLIP-CHIP DESIGNS Jin-Tai Yan, Zhi-Wei Chen 1 ASPDAC.2009.
GLARE: Global and Local Wiring Aware Routability Evaluation Yaoguang Wei1, Cliff Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi Reddy,
ARCHER:A HISTORY-DRIVEN GLOBAL ROUTING ALGORITHM Muhammet Mustafa Ozdal, Martin D. F. Wong ICCAD ’ 07.
B-Escape: A Simultaneous Escape Routing Algorithm Based on Boundary Routing L. Luo, T. Yan, Q. Ma, M. D.F. Wong and T. Shibuya Department of Electrical.
Configurable Multi-product Floorplanning Qiang Ma, Martin D.F. Wong, Kai-Yuan Chao ASP-DAC 2010.
Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng NTU &Synopsys An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs.
Escape Routing of Mixed-Pattern Signals Based on Staggered-Pin- Array PCBs K. Wang, H. Wang and S. Dong Department of Computer Science & Technology, Tsinghua.
1 A Min-Cost Flow Based Detailed Router for FPGAs Seokjin Lee *, Yongseok Cheon *, D. F. Wong + * The University of Texas at Austin + University of Illinois.
On Routing Fixed Escaped Boundary Pins for High Speed Boards T. Tsai, R. Lee, C. Chin and Y. Kajitani Global UniChip Corp. Hsinchu, Taiwan DATE 2011.
PARR:Pin Access Planning and Regular Routing for Self-Aligned Double Patterning XIAOQING XU BEI YU JHIH-RONG GAO CHE-LUN HSU DAVID Z. PAN DAC’15.
Timing-Driven Routing for FPGAs Based on Lagrangian Relaxation
Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations H.C. Ou, H.C.C. Chien and Y.W. Chang Electronics Engineering,
ILP-Based Inter-Die Routing for 3D ICs Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu Department of Electrical Engineering, National.
Maze Routing Algorithms with Exact Matching Constraints for Analog and Mixed Signal Designs M. M. Ozdal and R. F. Hentschke Intel Corporation ICCAD 2012.
BOB-Router: A New Buffering-Aware Global Router with Over-the-Block Routing Resources Yilin Zhang1, Salim Chowdhury2 and David Z. Pan1 1 Department of.
LEMAR: A Novel Length Matching Routing Algorithm for Analog and Mixed Signal Circuits H. Yao, Y. Cai and Q. Gao EDA Lab, Department of CS, Tsinghua University,
1 CS612 Algorithms for Electronic Design Automation CS 612 – Lecture 8 Lecture 8 Network Flow Based Modeling Mustafa Ozdal Computer Engineering Department,
An Exact Algorithm for Difficult Detailed Routing Problems Kolja Sulimma Wolfgang Kunz J. W.-Goethe Universität Frankfurt.
FPGA Routing Pathfinder [Ebeling, et al., 1995] Introduced negotiated congestion During each routing iteration, route nets using shortest.
XGRouter: high-quality global router in X-architecture with particle swarm optimization Frontiers of Computer Science, 2015, 9(4):576–594 Genggeng LIU,
EE4271 VLSI Design VLSI Channel Routing.
VLSI Physical Design Automation
2 University of California, Los Angeles
Routing Algorithms.
EE4271 VLSI Design, Fall 2016 VLSI Channel Routing.
Under a Concurrent and Hierarchical Scheme
Presentation transcript:

A Negotiated Congestion based Router for Simultaneous Escape Routing Q.Ma, T.Yan and Martin D.F. Wong Department of Electrical and Computer Engineering University of Illionis at Urbana- Champaign, USA ISQED 2010

Outline Introduction Problem Formulation Underlying Routing Graph Negotiated Congestion Application on Bus Untangling Experimental Results Conclusion

Introduction PCB routing is the problem of determining wiring connections between pin terminals on the circuit board. This paper focuses on a key problem in PCB routing called escape routing. The objective of escape routing is to route all terminal pins inside a component to the component boundaries.

Introduction There are several types of escape routing problems:  Single-component escape: route all pins inside a component to the component boundary without any constraint on the pin ordering  Ordered escape: one component, require the escape routing to conform to specified ordering along the boundary  Simultaneous escape: two components, the pin orderings of the escape routing for the two components are required to match each other in order to provide a planar topology for later detail routing between the components

Introduction

Problem Formulation Each routing tile has a horizontal capacity, vertical capacity and a diagonal capacity. cap(2,2,3) denotes the horizontal, vertical and diagonal capacities of a tile are 2, 2 and 3.

Problem Formulation Input:  Two components and the net number n, each component is a rectangular pin grid Objective:  Obtain detailed routing from these pins to the boundaries so that ordering of the escaped pins along two components’ boundaries match each other.  The escape routing inside the components is also required to satisfy the capacity constraints.

Underlying Routing Graph Graph model for a tile  Each node in this graph model can only accommodate one net. (the node capacity is 1)

Underlying Routing Graph cap(2,2,3)

Underlying Routing Graph This graph model correctly captures cap(2,2,3)

Underlying Routing Graph It can be easily modified to model the tile with cap(2,2,4)

Underlying Routing Graph The entire routing graph

Negotiated Congestion The negotiated congestion based routing scheme has been widely used in FPGA routing and global routing. In this routing scheme, routability is achieved by forcing all the nets to negotiate for a resource. Determine which net needs the resource most.

Negotiated Congestion The cost of a node v is computed by the following formula: b v : the base cost h v : the history cost p v : the number of nets currently occupying node v

Negotiated Congestion Initialize the cost Increase the history cost by Δ Every net is rip-up and reroute Increase Δ

Application on Bus Untangling Bus untangling problem: Given two columns of pins with labels {1..n} on each column Detour the pins to make the ordering match in the middle. The detouring must also satisfy the capacity requirement between adjacent pins in each column.

Application on Bus Untangling Two sides untangling can redistribute the occupied vertical tracks to two sides so that the max number of vertical tracks used on one side is reduced.

Application on Bus Untangling Some inputs may not have single detour solutions

Application on Bus Untangling View the bus untangling problem as a special case of the escape routing problem. Each pin column constitutes a component. Since NCER allows detours anywhere, the solution can have detours on both sides.

Experimental Results

Conclusion This paper studies the feasibility of applying negotiated congestion routing scheme to simultaneous escape routing problems. The two routers exhibit complementary behaviors.