03/12/07 Jon S Kapustinsky LANL Jon S Kapustinsky, LANL Forward Vertex Detector Collaboration Meeting UNM, March 12, 2007 Outline: FVTX Overall Description Sensor Details FPHX Details HDI Summary

03/12/07 Jon S Kapustinsky LANL Design Decisions Leading to the FVTX Sensor Wedge and FPHX Technical risk minimization the key driver Mini-strips maintain good resolution in r and phi with reasonable occupancy and manageable channel count Wire bonds replace initial idea to use bump bonds Chip placement moved from centerline of sensor to the edges minimizes potential noise coupling between chip and sensor facilitates implementation of decoupling between sensor bias and chip reference and avoids long path-length sensor return to ground Wedge assembly unit based on ease of assembly HDI designed to match standard industry capability Readout architecture of the FPHX draws heavily on previously designed FPIX, which we are currently working with for the LANL LDRD

03/12/07 Jon S Kapustinsky LANL Four stations of disks on each side One small disk (~60mm) three large disks (~126mm) Mini-strips of 75 micron radial pitch: mm Custom-designed FPHX readout chip from Fermilab (Yarema et. al.) Total strip count: 2 * 552,960 strips (zero suppressed) Total chip count: 2 * 4320 chips Forward Silicon Vertex Detector FVTX Wedges alternate front/back placement on disk

03/12/07 Jon S Kapustinsky LANL SensorHDI FPHX Chips (13 per column) FVTX Sensor Wedge (Prague, UNM, LANL) Not to Scale Sensor 2 columns of strips 1664 strips per column strip length ~2.8mm to ~11.2mm 75 micron spacing 48 wedges per disk (7.5˚/sensor, 15˚/wedge) 0.5 mm overlap with adjacent wedges FPHX Chip 1 column readout 128 channels ~ 70 microns channel spacing Dimensions – FNAL 9mm x 1.2 mm Mini-strips are oriented to approximate an arc

03/12/07 Jon S Kapustinsky LANL 6-inch wafer

03/12/07 Jon S Kapustinsky LANL Inner and outer wedges innerouter Vaclav Vrba, Institute of Physics, Prague, Czech Republic 4-inch wafer testing pads (both staged) bonding pads Guard ring Cutting edge

03/12/07 Jon S Kapustinsky LANL Narrow and wide wedges Four inner wedges on a waferThree outer wedges on a wafer Vaclav Vrba, Institute of Physics, Prague, Czech Republic 4-inch wafer

03/12/07 Jon S Kapustinsky LANL MATERIAL SPECIFICATION: Wafer diameter6 inch preferred (152 mm), 4 inch (100 mm) Crystal orientation or Thickness 300  m +10 μm –20 μm Resistivity: 2.0 – 5.0 kohm K  cm Uniformity of resistivity (wafer to wafer)  25% Passivation: Covering junction-side except for wire-bond pads and reference marks. It can either be silicon oxide or silicon nitride. DESIGN PARAMETERS: Devices are p-on-n dc-coupled mini-strips The full design for the masks will be provided by us in electronic form, GDS file format (Czech collaborators) Vendor will finalize the design details according to their design rules and process, and will work with us on the final design and mask layout.

03/12/07 Jon S Kapustinsky LANL Sensor Status Two column mini-strip 7.5˚ sensor geometry chosen Good resolution, reasonable occupancy and manageable channel count Draft mechanical design completed (LANL/Hytec) Based on ease of assembly Draft sensor design completed (Czech) Standard industry technology Preliminary price quotes from 2 vendors (more to follow) Micron, 6-inch CiS, 4-inch

03/12/07 Jon S Kapustinsky LANL Specifications Signal polarity: positive (holes) Gain at shaper output: 500 mV/fC 3-bit ADC Nominal peaking time: 60 ns Noise: 150e e/pF Power: 110 uW per channel for maximum input transistor bias current Imax: maximum tolerable input leakage current estimate 100nA/strip (programmable) 2.8% occupancy in central Au-Au All I/O pads are wire-bonded FPHX Chip (FNAL, LANL)

03/12/07 Jon S Kapustinsky LANL 60 nS peaking time 150 e noise floor 140 e/pf Integrator, CR-RC shaper, ADC FPHX Analog (Zimmerman, FNAL) Input to shaper Output of shaper 2 pf, max charge sharing, 25:1 S/N electrons Capacitance pf

03/12/07 Jon S Kapustinsky LANL Optimized to reduce noise coupling between sensor and readout chip Sensor HDI ground plane FPHX R/O chips Noise canceling digital supply loops Bypass cap to sensor backplane Noise canceling input signal loops

03/12/07 Jon S Kapustinsky LANL Figure - The output Data Word Phase 1Phase 2Phase 3Phase 4 Path 1/Event 1 HitSuppressSerialize Path 2/Event 2 SerializeHitSuppressSerialize Path 3/Event 3 Serialize HitSuppress Path 4/Event 4 SuppressSerialize Hit Data Push Architecture Simultaneous R/W Output up to 4 hits/event in 4 BCO’s FPHX digital (Hoff, FNAL)

03/12/07 Jon S Kapustinsky LANL FPHX Status (FNAL, LANL) Performance specifications provided by LANL to the FNAL design team Design completed by FNAL based on specifications provided Layout design and prototype run dependent on funding

03/12/07 Jon S Kapustinsky LANL HDI trace count 2 R/O lines x LVDS pair x 26 chips d’load and reset lines 4 2 clocks x LVDS pair 4 1 calibration line Analog and digital power and ground on imbedded layers High Density Interconnect (UNM, LANL) HDI Stack Up HDI 176 μm thick 4 copper planes (ground, power, 2ea signal), 5 Kapton films, 8 glue layers GND Signal Power

03/12/07 Jon S Kapustinsky LANL Sensor/ Kapton /Support assembly concept (Hytec)

03/12/07 Jon S Kapustinsky LANL HDI Status 15˚ wedge geometry determined for HDI Trace count defined based on FPHX design HDI placed between the sensor and the carbon support HDI will be designed to conform with industry standard capability Preliminary design has been FEA modeled for thermal performance

03/12/07 Jon S Kapustinsky LANL Summary Design decisions are driven by technical risk mitigation standard sensor technology readout chip based on existing design chip and sensor assembly optimized for noise immunity industry standard kapton HDI layout mechanical design based on ease of assembly

03/12/07 Jon S Kapustinsky LANL backup

03/12/07 Jon S Kapustinsky LANL Assumptions Ileak = I0 + (α x F) I0 = initial leakage current/ cm2 I0 ~ 1.8 μA/cm3 55nA/cm2 (scaled from 500 nA per 1x8 BteV tile) For a FVTX strip that is 1.3cm x.0075 cm x.03 cm = 3 x 10-4 cm3, I0 ~ 0.54 nA/strip α = damage constant ~ 2.5 x 10-17A/cm F = total fluence ~ 2 x 1013/cm2 (~500kRad) Ileak = 1.8 μA/cm3 + (2.5 x 10-17A/cm x 2 x 1013/cm2) = 52 μA/cm3 Istrip = 52 μA/cm3 x (3 x 10-4 cm3) = 15.6 nA/strip All the above is at room temperature Ileak(T2) = Ileak(T1) {T2/T1}2 exp {-E/2k(T1-T2/T1T2)} Temperatures in degrees Kelvin E ev K is the Boltzmann constant, x 10-5 ev/K At 0 degrees celsius, the leakage current would be reduced by ~ a factor of 7 None of the above accounts for annealing between run periods

03/12/07 Jon S Kapustinsky LANL 6-inch wafer