George Mason University ECE 449 – Computer Design Lab Welcome to the ECE 449 Computer Design Lab Spring 2005

2ECE 449 – Computer Design Lab Your TA – Monday & Tuesday section Milind M. Parelkar Office hours: TBD

3ECE 449 – Computer Design Lab Your TA – Thursday section Kamal Sayeed Office hours: Wednesday 7-9pm, Room 203

4ECE 449 – Computer Design Lab Lab meetings Venue: ST-II, Room 203 The first part of each class is reserved for a lecture given by the TA and the following hands-on session The second part of each class is reserved for the previous experiment demonstrations and the work on the new experiment

5ECE 449 – Computer Design Lab Lab policies Please refer to class website: ECE 449 Official Class Web Resources

6ECE 449 – Computer Design Lab Lab experiments (Part I, Individual) Combinational Logic – 7 Segment LED, etc. January 31- February 3 Sequential Logic – Blinking LEDs (Simulation) February 7-10 Sequential Logic – Blinking LEDs (Testing) February Finite State Machine – Sequence Detector February Finite State Machine – Pump Controller February 28-March 3

7ECE 449 – Computer Design Lab Lab experiments (Part II, Dual) Programmable Pulse Generator March March VGA Signal Generator April 4-7 April Microcontroller Core & Logic Analyzer April April May 2-5

8ECE 449 – Computer Design Lab Displaying Vertical Bars on the VGA screen End of Screen Color 1 Color 2 Color 64 Colors Repeat 8 pixels

9ECE 449 – Computer Design Lab 4 lines Color 1 Color 2 Color 64 Colors Repeat 4 lines Color 3 Color 4 Displaying Horizontal Bars on the VGA screen

10ECE 449 – Computer Design Lab Horizontal TraceHorizontal Flyback Vertical Flyback Generating pixels on the VGA monitor screen

11ECE 449 – Computer Design Lab VGA Control Signal Timing

12ECE 449 – Computer Design Lab Experiment 7: Top level view of the implemented circuit PIC µController FPGA PORTB PORTA 7-Seg Decoder PORTA Display PORTC = PORTC(0)STROBE CLK RESET

13ECE 449 – Computer Design Lab PICROM 256 x 12 Data Addr PROGRAM PCPC Instruction Decoder W ALU COMPUTATIONS CONSTANTS OPCODES Address Bus Data Bus 8 8 CONTROL UNIT MCLRCLK EXTENDED ALU PORTAPORTBPORTC 488 DATA FSR DinDout REGFILE R8 R31 Fsel PIC Microcontroller Core

14ECE 449 – Computer Design Lab Set Port Directions RESET Sum <= ‘0’ Counter <= ‘0’ Wait for a rising edge at Port C(0) Port B <= Port A Sum <= Sum + Port A Counter <= Counter + 1 Counter = 8? N Y Wait for a rising edge at Port C(0) Port B <= Sum(3 downto 0) Wait for a rising edge at Port C(0) Port B <= Sum(7 downto 4) Flowchart of our PIC program

15ECE 449 – Computer Design Lab Experiment 7-LA: Top level view of the implemented circuit PIC µController FPGA PORTB PORTA 7-Seg Decoder PORTA Display PORTC = PORTC(0)STROBE CLK RESET AddrData 8 8

16ECE 449 – Computer Design Lab Grading Lab Experiments (Part I)30% Midterm exam35% March 7, 8, 10 Lab Experiments (Part II)35%

17ECE 449 – Computer Design Lab Recommended Texts (1) Allen Dewey, Analysis and Design of Digital Systems with VHDL, 1997, PWS publishing, ISBN Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill © 2000 Edition: 1 ISBN:

18ECE 449 – Computer Design Lab Software ActiveHDL by Aldec used for design entry and simulation Synplify Pro by Synplicity used for logic synthesis Xilinx ISE by Xilinx Inc. used for implementation in Xilinx FPGA devices

19ECE 449 – Computer Design Lab Hardware XSA-100 boards with Xilinx Spartan 2 FPGA 2S100tq144 used in Spring 2004 New boards from Xilinx are likely to be used in Spring 2005

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