System Buses

Program Concept Hardwired systems are inflexible Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of control signals Instead of re-wiring, supply a new set of control signals

What is a program? A sequence of steps A sequence of steps For each step, an arithmetic or logical operation is done For each step, an arithmetic or logical operation is done For each operation, a different set of control signals is needed For each operation, a different set of control signals is needed

Function of Control Unit For each operation a unique code is provided For each operation a unique code is provided e.g. ADD, MOVEe.g. ADD, MOVE A hardware segment accepts the code and issues the control signals A hardware segment accepts the code and issues the control signals

Components The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit Data and instructions need to get into the system and results out Data and instructions need to get into the system and results out Input/outputInput/output Temporary storage of code and results is needed Temporary storage of code and results is needed Main memoryMain memory

Computer Components: Top Level View

Instruction Cycle Two steps: Two steps: FetchFetch ExecuteExecute

Fetch Cycle Program Counter (PC) holds address of next instruction to fetch Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Processor fetches instruction from memory location pointed to by PC Increment PC Increment PC Unless told otherwiseUnless told otherwise Instruction loaded into Instruction Register (IR) Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions Processor interprets instruction and performs required actions

Execute Cycle Processor-memory Processor-memory data transfer between CPU and main memorydata transfer between CPU and main memory Processor I/O Processor I/O Data transfer between CPU and I/O moduleData transfer between CPU and I/O module Data processing Data processing Some arithmetic or logical operation on dataSome arithmetic or logical operation on data Control Control Alteration of sequence of operationsAlteration of sequence of operations e.g. jumpe.g. jump Combination of above Combination of above

Example of Program Execution

Instruction Cycle State Diagram

Interrupts Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program Program e.g. overflow, division by zeroe.g. overflow, division by zero Timer Timer Generated by internal processor timerGenerated by internal processor timer Used in pre-emptive multi-taskingUsed in pre-emptive multi-tasking I/O I/O from I/O controllerfrom I/O controller Hardware failure Hardware failure e.g. memory parity errore.g. memory parity error

Program Flow Control

Interrupt Cycle Added to instruction cycle Added to instruction cycle Processor checks for interrupt Processor checks for interrupt Indicated by an interrupt signalIndicated by an interrupt signal If no interrupt, fetch next instruction If no interrupt, fetch next instruction If interrupt pending: If interrupt pending: Suspend execution of current programSuspend execution of current program Save context into STACK (memory)Save context into STACK (memory) Set PC to start address of interrupt handler routine (interrupt Vector)Set PC to start address of interrupt handler routine (interrupt Vector) Process interruptProcess interrupt Restore context and continue interrupted programRestore context and continue interrupted program

Transfer of Control via Interrupts Interrupt Vector

Instruction Cycle with Interrupts

Program Timing Short I/O Wait

Program Timing Long I/O Wait

Instruction Cycle (with Interrupts) - State Diagram

Multiple Interrupts Disable interrupts Disable interrupts Processor will ignore further interrupts whilst processing one interruptProcessor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processedInterrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occurInterrupts handled in sequence as they occur Define priorities Define priorities Low priority interrupts can be interrupted by higher priority interruptsLow priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interruptWhen higher priority interrupt has been processed, processor returns to previous interrupt

Multiple Interrupts - Sequential

Multiple Interrupts – Nested

Time Sequence of Multiple Interrupts

Connecting A computer consists of a set of components or modules of three basic types(up,mmry,I/O) that communicate with each other. A computer consists of a set of components or modules of three basic types(up,mmry,I/O) that communicate with each other. Different type of connection for different type of unit Different type of connection for different type of unit Memory: consists of N words of equal length. Each word is assigned a unique numerical address (0,1,…,N-1). A word of data can be read from or written into memory.Memory: consists of N words of equal length. Each word is assigned a unique numerical address (0,1,…,N-1). A word of data can be read from or written into memory. Input/Output : refer to each of the interface to an external device as a port and give each a unique address (e.g.,0,1,…M-1). There are external data paths for the input and output of data external device and I/O module may be able to send interrupt signals.Input/Output : refer to each of the interface to an external device as a port and give each a unique address (e.g.,0,1,…M-1). There are external data paths for the input and output of data external device and I/O module may be able to send interrupt signals. Processor : reads an instructions and data, writes out data after processing, and uses control signals to control the overall system and also receives interrupt.Processor : reads an instructions and data, writes out data after processing, and uses control signals to control the overall system and also receives interrupt.

Computer Modules

Memory Connection Receives and sends data Receives and sends data Receives addresses (of locations) Receives addresses (of locations) Receives control signals Receives control signals ReadRead WriteWrite TimingTiming

Input/Output Connection(1) Similar to memory from computer’s viewpoint Similar to memory from computer’s viewpoint Output Output Receive data from computerReceive data from computer Send data to peripheralSend data to peripheral Input Input Receive data from peripheralReceive data from peripheral Send data to computerSend data to computer

Input/Output Connection(2) Receive control signals from computer Receive control signals from computer Send control signals to peripherals Send control signals to peripherals e.g. spin diske.g. spin disk Receive addresses from computer Receive addresses from computer e.g. port number to identify peripherale.g. port number to identify peripheral Send interrupt signals (control) Send interrupt signals (control)

CPU Connection Reads instruction and data Reads instruction and data Writes out data (after processing) Writes out data (after processing) Sends control signals to other units Sends control signals to other units Receives (& acts on) interrupts Receives (& acts on) interrupts

Buses There are a number of possible interconnection systems There are a number of possible interconnection systems Single and multiple BUS structures are most common Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP) e.g. Unibus (DEC-PDP)

What is a Bus? A communication pathway connecting two or more devices A communication pathway connecting two or more devices Usually broadcast Usually broadcast Often grouped Often grouped A number of channels in one busA number of channels in one bus e.g. 32 bit data bus is 32 separate single bit channelse.g. 32 bit data bus is 32 separate single bit channels Power lines may not be shown Power lines may not be shown

Data Bus Provide a path for moving data between system modules. Provide a path for moving data between system modules. May consists of from 32 to hundreds of separate lines, number of lines refer to bus width and determines how many bits can be transferred at a time. May consists of from 32 to hundreds of separate lines, number of lines refer to bus width and determines how many bits can be transferred at a time. The width of the data bus is a key factor in determine overall performance. WHY? The width of the data bus is a key factor in determine overall performance. WHY?

Address bus Identify the source or destination of data Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory e.g. CPU needs to read an instruction (data) from a given location in memory Bus width determines maximum memory capacity of system Bus width determines maximum memory capacity of system e.g has 16 bit address bus giving 64k address spacee.g has 16 bit address bus giving 64k address space

Control Bus Transmit both command and timing information between system modules. Timing signal indicate the validity of data and address information. Command signal specify operations to be performed. Transmit both command and timing information between system modules. Timing signal indicate the validity of data and address information. Command signal specify operations to be performed. - Memory write: data on bus to be written into the adress location - Memory read: data from the addressed location to be placed on bus - I/O write: data on the bus to be output to the addressed I/O port - I/O read: data from the addressed I/O port to be placed on the bus - Transfer ACK: Indicate data has been accepted from or placed on the bus

Cont.. Bus request: indicates that a module needs to gain control of the bus Bus request: indicates that a module needs to gain control of the bus Bus grant: indicates that a requesting module has been granted control of the bus Bus grant: indicates that a requesting module has been granted control of the bus Interrupt request: indicates that an interrupt is pending Interrupt request: indicates that an interrupt is pending Interrupt ACK: Acknowledges that the pending interrupt has been recognized Interrupt ACK: Acknowledges that the pending interrupt has been recognized Clock: used to synchronize operations Clock: used to synchronize operations Reset: initializes all modules Reset: initializes all modules

Bus Interconnection Scheme

Physical Realization of Bus Architecture

Single Bus Problems Lots of devices on one bus leads to: Lots of devices on one bus leads to: Propagation delaysPropagation delays Long data paths mean that co-ordination of bus use can adversely affect performance Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity If aggregate data transfer approaches bus capacity Most systems use multiple buses to overcome these problems Most systems use multiple buses to overcome these problems

Traditional (ISA) (with cache)

High Performance Bus

Bus Types Dedicated Dedicated Separate data & address linesSeparate data & address lines Multiplexed Multiplexed Shared linesShared lines Address valid or data valid control lineAddress valid or data valid control line Advantage - fewer linesAdvantage - fewer lines DisadvantagesDisadvantages More complex control More complex control Ultimate performance Ultimate performance

Bus Arbitration More than one module controlling the bus More than one module controlling the bus e.g. CPU and DMA controller e.g. CPU and DMA controller Only one module may control bus at one time Only one module may control bus at one time Arbitration may be centralised or distributed Arbitration may be centralised or distributed

Centralised or Distributed Arbitration Centralised Centralised Single hardware device controlling bus accessSingle hardware device controlling bus access Bus Controller Bus Controller Arbiter Arbiter May be part of CPU or separateMay be part of CPU or separate Distributed Distributed Each module may claim the busEach module may claim the bus Control logic on all modulesControl logic on all modules

Timing Co-ordination of events on bus Co-ordination of events on bus Synchronous Synchronous Events determined by clock signalsEvents determined by clock signals Control Bus includes clock lineControl Bus includes clock line A single 1-0 is a bus cycleA single 1-0 is a bus cycle All devices can read clock lineAll devices can read clock line Usually sync on leading edgeUsually sync on leading edge Usually a single cycle for an eventUsually a single cycle for an event

Synchronous Timing Diagram

Asynchronous Timing – Read Diagram

Asynchronous Timing – Write Diagram

PCI Bus Peripheral Component Interconnection. Peripheral Component Interconnection. Develop in 1990 for Pentium-based system and released all patents to the public domain. Develop in 1990 for Pentium-based system and released all patents to the public domain. PCI may be configured as a 32 or 64 bit PCI may be configured as a 32 or 64 bit 49 mandatory signal lines. 49 mandatory signal lines.

Example of PCI configurations Typical desktop system

Exmple: Typical server system

PCI Bus Lines (required) Systems lines : include the clock and reset pins Systems lines : include the clock and reset pins Address & Data : include 32 lines that are time multiplexed for address and data. The other lines in this group are used to interpret and validate the signal lines that carry the address and data. Address & Data : include 32 lines that are time multiplexed for address and data. The other lines in this group are used to interpret and validate the signal lines that carry the address and data. Interface Control : control the timing of transactions and provide coordination among initiators and targets Interface Control : control the timing of transactions and provide coordination among initiators and targets Arbitration : these are not shared lines and each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter. Arbitration : these are not shared lines and each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter. Error lines : used to report parity and other error Error lines : used to report parity and other error

PCI Bus Lines (Optional) Interrupt pins : provide for PCI devices that must generate requests for service. Each PCI device has its own interrupt line or lines to an interrupt controller. Interrupt pins : provide for PCI devices that must generate requests for service. Each PCI device has its own interrupt line or lines to an interrupt controller. Cache support pin : these pins are needed to support a memory on PCI that can be cached in the processor or another device. Cache support pin : these pins are needed to support a memory on PCI that can be cached in the processor or another device. 64-bit bus extension pin : include 32 lines that are time multiplexed for address and data and that are combined with the mandatory address/data lines to form a 64-bit address/data bus. Other lines in this group are used to interpret and validate the signal lines that carry the address and data. There are two lines that enable two PCI devices to agree to use 64 bit capability. 64-bit bus extension pin : include 32 lines that are time multiplexed for address and data and that are combined with the mandatory address/data lines to form a 64-bit address/data bus. Other lines in this group are used to interpret and validate the signal lines that carry the address and data. There are two lines that enable two PCI devices to agree to use 64 bit capability. JTAG/boundary scan pins : These signal lines support testing procedures define in IEEE stabdard JTAG/boundary scan pins : These signal lines support testing procedures define in IEEE stabdard

PCI Commands Transaction between initiator (master) and target Transaction between initiator (master) and target Master claims bus Master claims bus Determine type of transaction Determine type of transaction e.g. I/O read/writee.g. I/O read/write Address phase Address phase One or more data phases One or more data phases

PCI Read Timing Diagram

PCI Bus Arbiter

PCI Bus Arbitration