Boolean Algebra and Logic Gates 1 Computer Engineering (Logic Circuits) Lec. # 10 (Sequential Logic Circuit) Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering Faculty of Engineering Zagazig University

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3 / 60 Sequential Circuits Combinational Circuit Memory Elements Inputs Outputs  Asynchronous  Synchronous Combinational Circuit Flip-flops Inputs Outputs Clock

4 / 60 Latches  SR Latch S R Q 0 QQ’ Q = Q0 Initial Value Transition Table Or Action Tble

5 / 60 Latches  SR Latch S R Q 0 Q Q’ Q = Q0 Transition Table Or Action Tble

6 / 60 Latches  SR Latch S R Q 0 Q Q’ Q = 0 Q = Q0 Transition Table Or Action Tble

7 / 60 Latches  SR Latch S R Q 0 Q Q’ Q = 0 Q = Q0 Q = 0 Transition Table Or Action Tble

8 / 60 Latches  SR Latch S R Q 0 Q Q’ Q = 0 Q = Q0 Q = 1 Transition Table Or Action Tble

9 / 60 Latches  SR Latch S R Q 0 Q Q’ Q = 0 Q = Q0 Q = 1 Transition Table Or Action Tble

10 / 60 Latches  SR Latch S R Q 0 Q Q’ Q = 0 Q = Q0 Q = 1 Q = Q’ 0 Transition Table Or Action Tble

11 / 60 Latches  SR Latch S R Q 0 Q Q’ Q = 0 Q = Q0 Q = 1 Q = Q’ 0 Transition Table Or Action Tble

12 / 60 Latches  SR Latch S RQ 0 Q0Q Q=Q’=0 No change Reset Set Invalid S R Q 0 Q=Q’= Q0Q0 Invalid Set Reset No change S’ R’

13 / 60 Latches  SR Latch S RQ 0 Q0Q Q=Q’=0 No change Reset Set Invalid S’ R’Q 0 Q=Q’= Q0Q0 Invalid Set Reset No change

14 / 60 Controlled Latches  SR Latch with Control Input C S RQ 0 x x Q0Q Q0Q Q=Q’Q=Q’ No change Reset Set Invalid

15 / 60 Controlled Latches  D Latch (D = Data) C DQ 0 x Q0Q No change Reset Set C Timing Diagram D Q t Output may change

16 / 60 Controlled Latches  D Latch (D = Data) C DQ 0 x Q0Q No change Reset Set C Timing Diagram D Q Output may change

17 / 60Flip-Flops  Controlled latches are level-triggered  Flip-Flops are edge-triggered C CLKPositive Edge CLKNegative Edge

18 / 60Flip-Flops  Master-Slave D Flip-Flop D Latch (Master) DCDC Q D Latch (Slave) DCDC QQD CLK D QMaster QSlave Looks like it is negative edge-triggered MasterSlave

19 / 60Flip-Flops  Edge-Triggered D Flip-Flop DQ Q DQ Q Positive Edge Negative Edge

20 / 60 Flip-Flops  JK Flip-Flop JQ QK D = JQ’ + K’Q

21 / 60 Flip-Flops  T- Flip-Flop D = TQ’ + T’Q = T  Q JQ QK T DQ Q T D = JQ’ + K’Q TQ Q

22 / 60 Flip-Flop Characteristic Tables DQ Q DQ(t+1) Reset Set JKQ(t+1) 00Q(t)Q(t) Q’(t) No change Reset Set Toggle JQ QK TQ Q TQ(t+1) 0Q(t)Q(t) 1Q’(t) No change Toggle

23 / 60 Flip-Flop Characteristic Equations DQ Q DQ(t+1) Q(t+1) = D JKQ(t+1) 00Q(t)Q(t) Q’(t) Q(t+1) = JQ’ + K’Q JQ QK TQ Q TQ(t+1) 0Q(t)Q(t) 1Q’(t) Q(t+1) = T  Q

24 / 60 Flip-Flop Characteristic Equations  Analysis / Derivation JQ QK JK Q(t)Q(t) Q(t+1) No change Reset Set Toggle

25 / 60 Flip-Flop Characteristic Equations  Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) No change Reset Set Toggle

26 / 60 Flip-Flop Characteristic Equations  Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) No change Reset Set Toggle

27 / 60 Flip-Flop Characteristic Equations  Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) No change Reset Set Toggle

28 / 60 Flip-Flop Characteristic Equations  Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) K 0100 J1101 Q Q(t+1) = JQ’ + K’Q

29 / 60 Flip-Flops with Direct Inputs  Asynchronous Reset DQ Q R Reset R’DCLKQ(t+1) 0xx0

30 / 60 Flip-Flops with Direct Inputs  Asynchronous Reset DQ Q R Reset R’DCLKQ(t+1) 0xx0 10 ↑ 0 11 ↑ 1

31 / 60 Flip-Flops with Direct Inputs  Asynchronous Preset and Clear PR’CLR’DCLKQ(t+1) 10xx0 DQ Q CLR Reset PR Preset

32 / 60 Flip-Flops with Direct Inputs  Asynchronous Preset and Clear PR’CLR’DCLKQ(t+1) 10xx0 01x x 1 DQ Q CLR Reset PR Preset

33 / 60 Flip-Flops with Direct Inputs  Asynchronous Preset and Clear PR’CLR’DCLKQ(t+1) 10xx0 01x x ↑ ↑ 1 DQ Q CLR Reset PR Preset

34 / 60 Analysis of Clocked Sequential Circuits 1.Determine number of flip flops 2.Determine number of Inputs 3.Determine the input equation for the F.F. (State Equation) 4.Draw a Transition Table. (PS-NS/ PI-PO) 5.Draw STD.

Analysis of Clocked Sequential Circuits 

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39 / 60 Analysis of Clocked Sequential Circuits  The State State = Values of all Flip-Flops Example A B = 0 0

40 / 60 Analysis of Clocked Sequential Circuits  State Equations A(t+1) = DA ( Not D. A ) = A(t) x(t)+B(t) x(t) = A x + B x B(t+1) = DB = A’(t) x(t) = A’ x y(t) = [A(t)+ B(t)] x’(t) = (A + B) x’

41 / 60 Analysis of Clocked Sequential Circuits  State Table (Transition Table) A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Input Next State Output ABxABy t+1 t t

42 / 60 Analysis of Clocked Sequential Circuits  State Table (Transition Table) A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy t+1 t t

State Transition Diagram (STD) 43 S0 Qa Qb 0 Y=0 & Z=1 X = 0 X = 1 State “Bubble” Transition Arc (For Input X=0) Transition Arc (For Input X=1) Input Variable (X) State (S0) Output Variables (Y & Z) State Variables (Qa & Qb)

44 / 60 Analysis of Clocked Sequential Circuits  State Diagram /00/0 0/10/1 1/01/0 1/01/0 1/01/0 1/01/00/10/1 0/10/1 AB input/output Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy

45 / 60 Analysis of Clocked Sequential Circuits  D Flip-Flops Example: DQ Q x CLK y A Present State Input Next State A xy A ,11 01,10 A(t+1) = DA = A  x  y

46 / 60 Analysis of Clocked Sequential Circuits  JK Flip-Flops Example: JA = BKA = B x’ JB = x’KB = A  x A(t+1) = JA Q’A + K’A QA = A’B + AB’ + Ax B(t+1) = JB Q’B + K’B QB = B’x’ + ABx + A’Bx’ Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB

47 / 60 Analysis of Clocked Sequential Circuits  JK Flip-Flops Example: Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB

48 / 60 Analysis of Clocked Sequential Circuits  T Flip-Flops Example: TA = B xTB = x y = A B A(t+1) = TA Q’A + T’A QA = AB’ + Ax’ + A’Bx B(t+1) = TB Q’B + T’B QB = x  B Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y

49 / 60 Analysis of Clocked Sequential Circuits  T -Flip-Flops Example: Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y /00/0 1/01/0 0/00/0 1/01/0 1/01/0 1/11/1 0/00/0 0/10/1