Background Motivation Implementation Conclusion 2.

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Presentation transcript:

Background Motivation Implementation Conclusion 2

Unlike FPGA, XOR Gate in ASIC Design has more delay and more area than other gates. We should reduce the number of XOR. 3 Gate Level FPGAASIC Logic Synthesis FPGAASIC RTL Level # of XOR ↑ # of XOR ↓

4 Which is the last area where people still manually optimize circuits, even though logic synthesis has made enormous progress. Is domination of a good arithmetic, however it contains a LARGE number of XORs.

5 But… Synthesizer seldom rewrites XORs… Automatically rewriting XORs is necessary for synthesizer! It is time to find a solution!

Why not rewrite all XORs? 6 1.Increase size of input expression exponentially. Only being used when number of XORs is small.

Why not rewrite all XORs? 7 2. Not all XORs are suitable for expansion: Before: D: 0.37ns A: 138.2um 2 After: D:0.26ns A: 146.9um 2 30% Faster! A Small Area Cost. Before: D: 0.22ns A: 58.8um 2 After: D:0.27ns A: 221.2um 2 Both Delay and Area Increases!

8 Local Correlation Global Correlation

9 Local Correlation Two Extreme Cases: AB=0=> A ⊕ B=A+B A+B=1 => A ⊕ B=AB So we consider AB and (A+B) as two important factors. We evaluate the delay and area of these two factors.

10 Local Correlation

11 Global Correlation

12 Global Correlation Much Faster Less Area Optimized Result

13 2 Correlations Merged Optimisation results for all benchmarks

14 2 Correlations Merged Comparison of bitwise delays of the multiplier Less Delay

15