Chapter 5 Boolean Algebra and Reduction Techniques 1

5-9 Karnaugh Mapping Used to minimize the number of gates –Reduce circuit cost –Reduce physical size –Reduce gate failures –Requires SOP form Karnaugh Mapping –Graphically shows output level for all possible input combinations – Moving from one cell to an adjacent cell, only one variable changes 31 2

Karnaugh Mapping Steps for K-map reduction: 1.Transform the Boolean equation into SOP form 2.Fill in the appropriate cells of the K-map 3.Encircle adjacent cells in groups of 2, 4 or 8 1.Adjacent means a side is touching, NOT diagonal. 2.Watch for the wraparound 4.Find each term of the final SOP equation by determining which variables remain the same within circles 33 3

Figure 5.86 Two-, three-, and four-variable Karnaugh maps. 4

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Figure 5.88 Encircling adjacent cells in a Karnaugh map. 6

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Discussion Point Use a K-map to simplify the circuit. 14

5-10 System Design Applications Use Karnaugh Mapping to reduce equations Use AND-OR-INVERT gates to implement logic 15

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Figure 5.96 (a) Simplified equation derived from a Karnaugh map; (b) implementation of the odd-number decoder using an AOI. 17

Summary Several logic gates can be connected together to form combinational logic. There are several Boolean laws and rules that provide the means to form equivalent circuits. Boolean algebra is used to reduce logic circuits to simpler equivalent circuits that function identically to the original circuit. 18

Summary DeMorgan’s theorem is required in the reduction process whenever inversion bars cover more than one variable in the original Boolean equation. NAND and NOR gates are sometimes referred to as universal gates, because they can be used to form any of the other gates. 19

Summary AND-OR-INVERT (AOI) gates are often used to implement sum-of-products (SOP) equations. Karnaugh mapping provides a systematic method of reducing logic circuits. Combinational logic designs can be entered into a computer using schematic block design software or VHDL. 20

Summary Using vectors in VHDL is a convenient way to group like signals together similar to an array. Truth tables can be implemented in VHDL using vector signals with the selected signal assignment statement. Quartus II can be used to determine the simplified equation of combinational circuits. 21