Controller Synthesis for Pipelined Circuits Using Uninterpreted Functions Georg Hofferek and Roderick Bloem. MEMOCODE 2011

Abstract  A novel abstraction-based approach for controller synthesis using logic with UF, arrays, equality, and limited quantification.  Extend Burch-Dill paradigm to synthesize the Boolean control for pipelined circuit.  Decide the controller existence by a reduction to propositional logic and extract the controller logic.

Problem Statement Registers / Memory f1f1 f2f2 fnfn c1c1 c2c2 cncn Controller Registers / Memory f1f1 f2f2 fnfn Non-pipelined processor: Pipelined processor, using the same combinational datapath elements:

Preliminary – Array Property Fragment  Write axiom  Properties of array with uninterpreted indices  F: index guard G: value constraint  Index guard grammar:  Array properties  uninterpreted function (Bradley et al. [7])

Preliminary – Uninterpreted Function  A function  Mapping input value(s) to output value  Uninterpreted  Do not care about its explicit mapping  Care functional consistency  UF  equality logic (Ackermann’s reduction [1])

Preliminary – Equality Logic  First-order logic with one special predicate “=“  x 1 = x 2 Λ x 2 = x 3 Λ x 4 = x 5 Λ x 5  x 1  Equality logic  propositional logic (Bryant & Velev [8]) x1,x2,x3x1,x2,x3 x4,x5x4,x5

Equivalence Pipelined Architecture Non-Pipelined Architecture complete step Instr. Set Arch. (ISA) Burch-Dill paradigm: Instruction Set Architecture Pipelined Architecture

A simple example Registers REG ALU c ontrol v w d est s ource Read Write Registers REG ALU s ource d est Read Write Non-pipelined Architecture (=reference): Pipelined Architecture:

Equivalence Criterion Registers REG ALU c ontrol v w Read Write s ource d est

Synthesis Approach & Reduction  Claim: AUE  UE UE  E E  Prop. logic

Reduction – AUE  UE 1. Replace Array-Writes with fresh variables and apply write axiom 2. Replace universal quantifications with conjunction over index set 3. Replace Array-Reads with uninterpreted functions

Reduction – UE  E  Replace all function instances with fresh variables  Add functional consistency constraints

Reduction – E  Prop. Logic  Replace equalities with fresh Boolean variables to obtain  Compute transitivity constraints from (chordal) equality graph

Extract Control Logic  We started from:  Apply transformations, obtain  Universally quantify “next states”  May blow up the size of BDD, but average cases are okay  Expand existential quantification of   Find cofactors of  On set:  Off set:  DC set:  Find function in this interval Don’t-Care-Set OFF-Set ON-Set Solution

Results  Complexity  Reduction: polynomial time  Computing the quantification: exponential time w.r.t #var.  Total: worst-case exponential time  Proof-of-concept  10 minutes with dynamic reordering  Validate using z3 SMT solver  c  ( s = w )

AUE  UE 2012/9/13

Outline  Quick review  AUE  UE reduction  Back to controller synthesis

Problem Statement Registers / Memory f1f1 f2f2 fnfn c1c1 c2c2 cncn Controller Registers / Memory f1f1 f2f2 fnfn Non-pipelined processor: Pipelined processor, using the same combinational datapath elements:

Equivalence Criterion Registers REG ALU c ontrol v w Read Write s ource d est

Synthesis Approach  Define equivalence criterion:  Claim:  If the claim is valid, extract Registers REG ALU c ontrol v w d est s ource Read Write

Synthesis Approach & Reduction  Claim: AUE  UE UE  E E  Prop. logic

Array Property Fragment  Decidable fragment that allow some quantification  Specify basic properties of arrays, not just properties of array elements  Properties of array with uninterpreted indices  F: index guard G: value constraint  Index guard grammar:  Example

Reduction Example  Apply write axiom  Index set  Replace universal quantification by conjunction

Reduction Example  Expand  Simplify

Reduction Example  Distinguish lambda from other members of I  Simplify

Back to Controller Synthesis  Claim:  Lambda constraint: AUE  UE