PROJECT GUIDE GROUP MEMBERS Dr.B.GOPI,B.E.M.E.Ph.D P.MENAKA G.NIVEDHA M.PAVITHRA M.POORNIMA G.PRIYA 1
A numerical study on performance of MOSFET is analyzed. The drain current value of MOSFET can be reduced by varying substrate, gate and gate oxide materials. By reducing the drain current ( I d ), the power dissipation can be reduced. Thus the performance of the device can be increased by reducing the drain current ( I d ). 2
Single gate MOSFET Output characteristics Transfer characteristics On state Resistance Power dissipation 3
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SUBSTRATE MATERIALS Silicon Germanium GATE MATERIAL Aluminium GATE OXIDE MATERIALS Silicon di oxide Hafnium oxide Air 5
I d =k n W/L((V gs -V T )V ds -(V ds 2 /2)) k n =C ox µ n Where I d – drain current k n - process parameter W-width of gate L-length of gate V gs – gate source voltage V T - threshold voltage V ds - drain source voltage C ox - gate oxide capacitance µ n - charge carrier effective mobility 6
Output characteristics is a plot between drain voltage(V DS ) and drain current(I D ) by keeping gate voltage(V GS ) constant. CUTOFF REGION: I D =0 LINEAR REGION : I D = µ n C 0x W/L ((V GS -V T )V DS -(V DS 2 /2)) 7
SATURATION REGION : I D =0.5 µ n C 0x W/L(V GS- V T ) 2 µ n – mobility C 0X – capacitance of oxide layer C 0X – (ε 0 ε r )/t 0x ε 0 –permittivity of free space ε 0 –8.854*10^-12 ε r –relative permittivity 8
9 V ds (2V) I D (A) V ds (3V) I D (A) V ds (4V) I D (A) V ds (5V) I D (A) V ds (6V) I D (A) 05.01E E E E E
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R ON = 1/(μ n C OX W/L)(V gs -V ds -V T ) μ n -charge carrier effective mobility C OX - gate oxide capacitance W –width of the gate L-length of the gate V gs – gate source voltage V T - threshold voltage V ds - drain source voltage 11
12 I d (A)RON2(Ω)I d (A)RON3(Ω)I d (A)RON4(Ω)I d (A)RON5(Ω)I d (A)RON6(Ω) 5.01E E E E E
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P D = I D 2 R ON I D = drain current R ON = ON state resistance 14
15 I d (A)Pd2(W) I d (A)Pd3(W) I d (A)Pd4(W) I d (A)Pd5(W) I d (A)Pd6(W) 5.01E E E E E E E
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Output characteristics is a plot between gate voltage (V GS ) and drain current(I D ) by keeping drain voltage(V DS ) constant 17
18 Gate voltage(V)Drain current (A) 01.44E E E E E E
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“ HYBRID Ge-Si BASED MOSFET DEVICES” in the “International Journal of Electrical, Electronics and Computer System (IJEECS)” “ VARIATION OF GATE MATERIALS FOR HYBRID GE-SI MOSFET” in the “International Journal of Nanotechnology and Application journal” 20
“HYBRID AlGaAs-SI BASED MOSFET DEVICES” in the “IOSR Journal of vlsi and signal processing” “TRI-GATE STRUCTURE TO REDUCE DRAIN CURRENT” in “International Journal Of Electrical, Electronics and Telecommunication Engineering Recent Science Publications” 21
“ ANALYSING THE PERFORMANCE OF MOSFET BY VARYING THE SUBSTRATE MATERIALS” in “Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE)” “COMPARATIVE STUDY ON THE PERFORMANCE OF MOSFET WITH GOLD AND SILVER AS GATE MATERIALS” in “IMPACT :International Journal of Research in Engineering & Technology ” 22
We have obtained output characteristics, transfer characteristics, ON resistance, power dissipation for MOSFET by changing the substrate and gate materials. Thus the power dissipation of MOSFET is reduced with the help of reducing the drain current and the performance of the device is increased through this. 23
H. Iwai, Extended Abstracts th International Workshop on Junction Technology (IWJT '08) (Shanghai, China 2008 May 15-16, IEEE Press) p. 1. [DOI: /IWJT ]. International Technology Roadmap for Semiconductors (ITRS) 2007 Edition. Available from: B. Razavi, Design of Analog CMOSIntegrated Circuits (McGraw-Hill, Boston,MA, 2001). R. F. Pierret, Semiconductor Device Fundamentals (Addison- Wesley, Reading,MA, 1996) p
J. Appenzeller et al., “Scheme for the fabrication of ultrashort channel MOSFETs,” Appl. Phys. Lett., vol. 77, pp. 298–300, July 2000 B. Yu et al., “15 nm gate length planar CMOS transistor,” in IEDM Tech.Dig., 2001, pp. 937–