 Seattle Pacific University EE Logic System DesignMemory-1 Memories Memories store large amounts of digital data Each bit represented by a single storage cell Major Categories Static RAM (SRAM) Dynamic RAM (DRAM) Mask-programmed ROM Erasable, Programmable ROM (EPROM) Electrically Erasable ROM (EEROM)

 Seattle Pacific University EE Logic System DesignMemory-2 Memory Bit Cells Static RAM Each bit is stored in a D latch write bit In bit Out Dynamic RAM Each bit is stored in a capacitor bit In bit Out wrrd bit In bit Out read write GND Note: In real implementations, tri-state inverters are replaced with single NMOS transistors DQ en write bit In bit Out

 Seattle Pacific University EE Logic System DesignMemory-3 Multi-bit Registers A Register combines several bit cells in one package wr bit In bit Out Bitcell bit In [3] bit Out [3] bit In [2] bit Out [2] bit In [1] bit Out [1] bit In [0] bit Out [0] write wr bit In bit Out Bitcell wr bit In bit Out Bitcell wr bit In bit Out Bitcell Registers usually come in 4-, 8-, or 16-bit sizes Anything bigger takes too many I/O pins A 1K-bit register requires over 2000 pins Asynchronous Uses D-latches enabled by the write signal Synchronous Uses D-FF’s Common write signal Must write all bits at the same time

 Seattle Pacific University EE Logic System DesignMemory-4 Addressable Memories Registers have two drawbacks 1. In order to write one bit, you have to write them all 2. Large memories require millions of pins Assign a number (address) to each bit cell Input the address to read/write Access one bit at a time (for read or write) Address [9..0] Data Out Data In Write 1024-bit Memory 10-bit address (2 10 = 1024) 1 bit of data read/written at a time Write signal controls whether reading or writing No clock: Data may be read/written at any time Clock: Inputs are looked at on rising edge of clock

 Seattle Pacific University EE Logic System DesignMemory-5 Addressing write Address N=2 n Data bits n Address inputs n-to-2 n Decoder... O0O0 O1O1 ONON en Data In Address Data Out... I0I0 I1I1 ININ 2 n -to-1 Mux Z wr bit In bit Out Bitcell wr bit In bit Out Bitcell wr bit In bit Out Bitcell sel 0 sel 1 sel N

 Seattle Pacific University EE Logic System DesignMemory-6 Selectable Bit Cells wr bit In bit Out Bitcell bit In bit Out write sel Add a select input: Bitcell activated only when selected To replace the output multiplexor with a bus, we must add logic to turn on the output of a bit cell only when selected From common DataIn Line To common DataOut Line (Tri-state) From Individual Select Line From Common Write Line wr bit In bit Out Bitcell sel 

 Seattle Pacific University EE Logic System DesignMemory-7 Memory with Selectable Bit Cells N=2 n Data bits Data In memSelect Address n-to-2 n Decoder... O0O0 O1O1 ONON en sel 0 sel 1 sel N Data Out  write This is a tri-state  bus - Only one bit cell is driving it at any time Memory select – if memory is not selected, Data Out is tri-stated wr bit In bit Out Bitcell sel  wr bit In bit Out Bitcell sel  wr bit In bit Out Bitcell sel  Address [n-1..0] Data Out  Data In Write 2 n -bit Memory memSelect

 Seattle Pacific University EE Logic System DesignMemory-8 Bi-directional Bit Cells The bitOut line is already tri-state – it can be an input or an output! We’ll never be reading and writing at the same time – why not combine the bit In and bit Out lines… To common Data In/Out Line (Tri-state) From Individual Select Line From Common Write Line Bitcell wr bit sel  wr bit In bit Out Bitcell bit  write sel Make sure that the bit line is not driven when writing

 Seattle Pacific University EE Logic System DesignMemory-9 Memory with Bi-directional Data Line N=2 n Data bits Data  Write asserted: Input Otherwise: Output Address [n-1..0] Data  Write 2 n -bit Memory memSelect Address n-to-2 n Decoder... O0O0 O1O1 ONON en sel 0 sel 1 sel N write Bitcell wr bit sel  Bitcell wr bit sel  Bitcell wr bit sel 

 Seattle Pacific University EE Logic System DesignMemory-10 Memory with Multi-bit Words (4-bit word example) Address Data 3  memSelect n-to-2 n Decoder... O0O0 O1O1 ONON en sel 0 sel 1 sel N write Bitcell wr bit sel  Bitcell wr bit sel  Bitcell wr bit sel  Data 2  Bitcell wr bit sel  Bitcell wr bit sel  Bitcell wr bit sel  Data 1  Bitcell wr bit sel  Bitcell wr bit sel  Bitcell wr bit sel  Data 0  Bitcell wr bit sel  Bitcell wr bit sel  Bitcell wr bit sel  Address [n-1..0] Data  [W-1..0] Write 2 n xW-bit Memory memSelect W Bits Wide Repeat bit columns for wider memories: - Sel common for each row - Write common for all bits - Data common for each column

 Seattle Pacific University EE Logic System DesignMemory-11 Static Memories Real SRAMs come in a variety of sizes, but are based on the same basic principles Address input specifies where to read/write Data input/output contains data to read or write A 0 -A 10 D 0 -D 7 OE* CS* WE* 6116P-4 SRAM Bytewide 2K x 8-bit: 24 pins A 0 -A 13 D0D0 OE* CS* WE* 6167 SRAM Bitwide 16K x 1-bit: 20 pins WE* (write enable): 1 for reads, 0 for writes OE* (output enable): 0 enables the output drivers CS* (chip select): 0 to select the chip (enable it)

 Seattle Pacific University EE Logic System DesignMemory-12 Bitwide vs. Bytewide Bytewide chips provide a complete byte at a time Perfect for microcontroller systems Bitwide chips provide only one bit at a time We usually need a whole byte (or more) Requires putting eight or more chips together Common addressing for all chips Each chip provides a single bit Example: 32-bit wide memory needs 32 chips Bitwide chips make sense only when we’re going to have to use a lot of chips anyway (i.e. large systems)

 Seattle Pacific University EE Logic System DesignMemory A Read Cycle Timing Diagram A 00 -A 12 D0D7D0D7 t RC t AA t CO1 ParameterMinMax CS1* OE* t LZ1 t OE t OLZ t OH t HZ1 Data Valid Address Valid t OE Output enable to data valid60ns t RC Read Cycle time120ns t AA Address Access time120ns t C01 CS1 to data valid120ns t OLZ Output enable to data bus driven5ns t OH Output hold after address change10ns t LZ1 CS1 to data bus driven10ns t HZ1 CS1 unasserted to data Hi-Z0ns40ns t OHZ If OE* is tied low, then use t CO1 and t LZ1

 Seattle Pacific University EE Logic System DesignMemory-14 Dynamic RAM Bit Cell bit In bit Out read write GND Replace Tri-state inverter with a single nMOS transistor. Use bi-directional bit line. bit In bit Out wrrd bitsel  bit sel GND  Reading: Don’t drive bit line; select bit cell. Writing: Externally drive bit line (hi/lo); select bit cell.

 Seattle Pacific University EE Logic System DesignMemory-15 Destructive Read A memory cell is read by discharging the capacitor Only a small voltage change Destroys the value held in the cell! A Sense-Amp senses the small voltage changes and amplifies them Once amplified, the value is written back to the memory cell SA write or writeback bit line (connected to all bits in column) bit sel GND  bitcell rowsel  write’

 Seattle Pacific University EE Logic System DesignMemory bit DRAM Organization Row Enable 0 Row Enable 1 Row Enable 2 Row Enable 3 Sense Amps ColSel 0 ColSel 1 ColSel 2ColSel 3 DRAMs are organized as square arrays ½ address bits for row, ½ for column In this 16-bit memory: 2 bits for row, 2 for col The row is selected first, reading all columns in row The column is then selected at the bottom All bits in row are written back Example: Read location 6 (0110) Row = 01, Col = 10

 Seattle Pacific University EE Logic System DesignMemory-17 Refresh Row Enable 0 Row Enable 1 Row Enable 2 Row Enable 3 Sense Amps ColSel 0 ColSel 1 ColSel 2ColSel 3 DRAM loses its charge in a few milliseconds Have to re-write every 20ms or so Reading every bit will do (writeback will refresh) This means 64M reads every 20ms for a 64Mb DRAM Solution: Reading just one bit in a row causes all to be refreshed! Only sqrt(64M) = 8K reads per 20ms

 Seattle Pacific University EE Logic System DesignMemory-18 DRAM Pinout A 64M x 1 DRAM needs: 26 Address Pins,1 Data Pin,CS*,R/W*,OE,Vdd, GND 26 out of 32 pins are just for the address! Break the address up into two parts Row and Column Load in the Row first, and latch it Load in the Column second Use RAS* and CAS* to indicate each half of the address

 Seattle Pacific University EE Logic System DesignMemory-19 DRAM timing Address RAS* Data t RC CAS* t RAC RowCol 1. Place Row address on bus, Assert RAS* 2. Place Col address on bus, Assert CAS* 3. Wait for data to become valid (t RAC ), Read Data 4. Wait for writeback to complete (t RC ), start next cycle Data

 Seattle Pacific University EE Logic System DesignMemory-20 Memory Type Comparisons Any data that needs to persist after power off Program memory for special- purpose systems Large memories for computers 1. High-speed memory 2. Small memories Uses Non-volatile (may have limits) IndestructibleErased on Power off Volatility CheapestCheapCheapestExpensivePrice Slow (read – 100ns) (write – 4700ns) Varies Slow (15ns min access time) Access modes speed up (DDR SDRAM, etc.) Fastest (3ns min access time) Speed EEROMROMDRAMSRAM