CSCI 136 Lab 1: 135 Review.

Slides:



Advertisements
Similar presentations
Integer Arithmetic: Multiply, Divide, and Bitwise Operations
Advertisements

Review of the MIPS Instruction Set Architecture. RISC Instruction Set Basics All operations on data apply to data in registers and typically change the.
CS/COE0447 Computer Organization & Assembly Language
Machine Instructions Operations
INSTRUCTION SET ARCHITECTURES
Machine Instructions Operations 1 ITCS 3181 Logic and Computer Systems 2015 B. Wilkinson Slides4-1.ppt Modification date: March 18, 2015.
10/9: Lecture Topics Starting a Program Exercise 3.2 from H+P Review of Assembly Language RISC vs. CISC.
CS3350B Computer Architecture Winter 2015 Lecture 4
Computer Structure - Computer Arithmetic Goal: Representing Numbers in Binary  Base 10 (decimal) - Numbers are represented using 10 numerals: 0, 1, 2,
Comp Sci instruction encoding 1 Instruction Encoding MIPS machine language Binary encoding of instructions MIPS instruction = 32 bits Three instruction.
ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 4: Arithmetic / Data Transfer Instructions Partially adapted from Computer Organization.
Computer Architecture CPSC 321 E. J. Kim. Overview Logical Instructions Shifts.
S. Barua – CPSC 440 CHAPTER 2 INSTRUCTIONS: LANGUAGE OF THE COMPUTER Goals – To get familiar with.
RISC Concepts, MIPS ISA and the Mini–MIPS project
Logical & shift ops (1) Fall 2007 Lecture 05: Logical Operations.
Lecture 5 Sept 14 Goals: Chapter 2 continued MIPS assembly language instruction formats translating c into MIPS - examples.
ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 6: Logic/Shift Instructions Partially adapted from Computer Organization and Design, 4.
ECE 4436ECE 5367 ISA I. ECE 4436ECE 5367 CPU = Seconds= Instructions x Cycles x Seconds Time Program Program Instruction Cycle CPU = Seconds= Instructions.
CSCI 136 Lab 1 Outline Go through the CD attached to the textbook. Homework Hints 135 Review.
Some material taken from Assembly Language for x86 Processors by Kip Irvine © Pearson Education, 2010 Slides revised 2/2/2014 by Patrick Kelley.
CMPE 325 Computer Architecture II Cem Ergün Eastern Mediterranean University Integer Representation and the ALU.
1  2004 Morgan Kaufmann Publishers Instructions: bne $t4,$t5,Label Next instruction is at Label if $t4≠$t5 beq $t4,$t5,Label Next instruction is at Label.
IT253: Computer Organization Lecture 5: Assembly Language and an Introduction to MIPS Tonga Institute of Higher Education.
CSE378 Instr. encoding.1 Instruction encoding The ISA defines –The format of an instruction (syntax) –The meaning of the instruction (semantics) Format.
Lecture 8. MIPS Instructions #2 – Memory Access (Load/Store) Instructions Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer.
Chapter 10 The Assembly Process. What Assemblers Do Translates assembly language into machine code. Assigns addresses to all symbolic labels (variables.
Computer Organization and Architecture Instructions: Language of the Machine Hennessy Patterson 2/E chapter 3. Notes are available with photocopier 24.
CPS3340 COMPUTER ARCHITECTURE Fall Semester, /08/2013 Lecture 10: MIPS Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER SCIENCE CENTRAL STATE.
True Assembly Language Part I. The Assembly Process The process of translating a MAL code (an assembly language program) into machine code (a sequence.
Chapter 2 CSF 2009 The MIPS Assembly Language. Stored Program Computers Instructions represented in binary, just like data Instructions and data stored.
Computer Organization CS224 Fall 2012 Lessons 7 and 8.
Chapter 2 — Instructions: Language of the Computer — 1 Memory Operands Main memory used for composite data – Arrays, structures, dynamic data To apply.
DR. SIMING LIU SPRING 2016 COMPUTER SCIENCE AND ENGINEERING UNIVERSITY OF NEVADA, RENO Session 7, 8 Instruction Set Architecture.
CMPUT Computer Organization and Architecture I1 CMPUT229 - Fall 2003 Topic6: Logic, Multiply and Divide Operations José Nelson Amaral.
Arrays in MIPS Assembly Computer Organization and Assembly Language: Module 6.
Csci136 Computer Architecture II Lab#5 Arithmetic Review ALU Design Ripple Carry Adder & Carry lookahead HW #4: Due on Feb 22, before class Feb.16, 2005.
Pirouz Bazargan SabetDecember 2003 Effective Implementation of a 32-bit RISC Processor Pirouz Bazargan Sabet University of Paris 6 - LIP6 - ASIM
MIPS Arithmetic and Logic Instructions
COMPUTER ARCHITECTURE & OPERATIONS I Instructor: Yaohang Li.
Computer Architecture & Operations I
Computer Architecture & Operations I
MIPS Instruction Set Advantages
Integer Multiplication and Division
Morgan Kaufmann Publishers
ELEN 468 Advanced Logic Design
RISC Concepts, MIPS ISA Logic Design Tutorial 8.
Instructions - Type and Format
Lecture 4: MIPS Instruction Set
MPIS Instructions Functionalities of instructions Instruction format
MISP Assembly.
CSCI206 - Computer Organization & Programming
The University of Adelaide, School of Computer Science
Computer Architecture & Operations I
ECE232: Hardware Organization and Design
Chapter 2 Instructions: Language of the Computer
Instruction encoding The ISA defines Format = Encoding
MIPS Assembly.
Computer Instructions
Computer Architecture
Instruction encoding The ISA defines Format = Encoding
UCSD ECE 111 Prof. Farinaz Koushanfar Fall 2018
Instruction encoding The ISA defines Format = Encoding
MIPS Assembly.
Instruction encoding The ISA defines Format = Encoding
MIPS assembly.
Review In last lecture, done with unsigned and signed number representation. Introduced how to represent real numbers in float format.
CS352H Computer Systems Architecture
MIPS Arithmetic and Logic Instructions
MIPS Arithmetic and Logic Instructions
MIPS instructions.
Presentation transcript:

CSCI 136 Lab 1: 135 Review

Our machine uses 32 bit memory addresses. A memory address refers to a single byte in memory. (“Byte Addressable”) 00000000 00000000 10000000 00000000 0x00000000 Memory 0xFFFFFFFF

But our data path out of memory is designed to move 32 bit words (or multiples of 32 bits) at a time. 0x00000000 Data Path Memory 0xFFFFFFFF Life is simpler and we get MUCH better performance if we divide memory in to 4 byte chunks (“words”) and always access these word size chunks.

00 This is called “Word Alignment” Memory 0x00000000 Data Path Memory 0xFFFFFFFF An address is “word aligned” if its 2 least significant bits are 0… (and thus is divisible by 4) 00 Disclaimer: You can use lb (load byte) and sb (store byte) to get a specific byte… but these commands are slow and often use lw (load word) and sw (store word) “inside the machine” along with a couple other commands to implement lb and sb.

Accessing Bytes When might we use lb (load byte) and sb (store byte)?

Assume 32 bit word: Big Endian vs. Little Endian Byte Ordering Assume 32 bit word: Big Endian vs. Little Endian Byte address: 0x00000000 Byte address: 0x00000001 Byte address: 0x00000002 Byte address: 0x00000003 00000000 00000000 10000000 00000000 On a Big Endian machine the Most Significant Byte (MSB) of a 32 bit word is stored at the lowest memory address. What is this number on a Big Endian machine?

Byte Ordering Byte address: 0x00000000 Byte address: 0x00000001 Byte address: 0x00000002 Byte address: 0x00000003 00000000 00000000 10000000 00000000 On a Little Endian machine the Most Significant Byte (MSB) of a 32 bit integer is stored at the highest memory address. What is the above integer on a Little Endian machine? Byte address: 0x00000000 Byte address: 0x00000001 Byte address: 0x00000002 Byte address: 0x00000003 00000000 00000000 00000000 10000000 What is the above integer on a Little Endian machine? What is it on a Big Endian machine?

Byte Ordering Computer designers can’t seem to agree on whether to use Big Endian or Little Endian. Neither design is really superior to the other. What kind of Endian are Intel PCs? What kind of Endian are Macs? Sun SPARC Stations can be set in either mode… (but Solaris OS requires Big Endian). Most of the time.. you probably won’t notice Endianness. But SPIM simulator uses the “Endianness” of the machine you run it on!

Where does it matter? When does “Endianness” matter? We will grade projects using PCSpim. If you use a Mac or XSPIM on Sun, make sure you test on a PC before submitting.

Load Immediate (li) li $t0, 4 lui $t0, 0 ori $t0, $t0, 4 What does the following instruction do? li $t0, 4 What does the following sequence of instructions do? lui $t0, 0 ori $t0, $t0, 4

li (load immediate) instruction is really “pseudocode” When the assembler sees an li instruction it substitutes: lui (load upper immediate) followed by an ori (or immediate) In the place of the li (load immediate) We’ll use li in the next few examples

Binary and Hex Review What is 0xAF (32 bit word) in decimal? What is 23 in binary?

2’s Complement Numbers To get negative number from a positive.. Invert all digits and add 1. To get a positive number from a negative… Invert all digits and add 1. Assume 8 bit word. What is -57 in 2’s complement notation? How do we do change a number’s sign in assembly language?

Sign Extension Sign extension can be used when you shift a register right… the sign bit is repeated to keep a negative number negative… This is referred to as “Arithmetic” variety of shift If the sign bit isn’t extended.. (i.e. empty spots filled with 0s) then the shift is called “Logical” variety of shift

Assume 8 bit words… What is result of logical right shifting -11 by 2? assembly: srl (shift right logical) srlv (shift right logical variable) What is result of arithmetic right shift -11 by 2? assembly: sra (shift right arithmetic) srav (shift right arithmetic variable) What is result of rotate right -11 by 2? assembly: ror (rotate right) What is the assembly code to do this?

What is result of rotating left -11 by 2? assembly: rol (rotate left) What is the result of logical shift left -11 by 2? assembly: sll (shift left logical) sllv (shift left logical variable) What is the assembly code to do this? Why isn’t there a sla (shift left arithmetic) assembly instruction?

Useful Shifts Considering an 8 bit word… how would we compute dividing -6 by 2? Consider an 8 bit word… how would we compute multiplying -7 by 4?

Useful Shifts Shifts are fast. Compilers will often substitute shifts for multiplication and division of integers by powers of 2. Note that rotate instructions require that rotation amount be supplied by a register. There is no “shift amount” constant value in a rotate instruction.

MIPS Adding and Subtracting What does following instruction do? add $t1, $t2, $t3 How about the following? addi $t1, $t2, 4 sub $t1, $t2, $t3

What is Overflow? Consider unsigned 8 bit integers.. What happens when we add 0x73 and 0xA9 ? Can we get overflow when we add a positive and a negative number? Consider signed 8 bit (2’s complement) integers.. what happens when we add 0xBC and 0xB0?

Multiplication Math Review What is result of multiplying unsigned integers 0xF and 0xF? If we multiply two 32 bit unsigned integers… what is the size in bits of the largest possible result?

Multiplication Instruction What does the following do? mul $t2, $t3 What do mfhi (move from hi) and mflo (move from lo) instructions do? What does the following instruction do? mul $t5, $t7, $t3

Memory Space In our SPIM simulator memory space, what percentage of our memory is reserved for the OS? With 32 bit addresses and byte addressing… how much memory can our machine have?

Offsets in lw and sw In our lw (load word) and sw (store word) instructions we can only supply a 16 bit offset. This offset is sign extended. What does this command do? lw $s0, 0x0004($t0) lw $s0, 0xFFFC($t0) How many bytes can offset?

Global Pointer ($gp) Where does our data segment begin? If we want to load the word stored at 0x10010020 the following code would be required: lui $s0,0x1001 # What does this do? lw $s1,0x0020($s0) # and this? This is kind of inefficient. We’re always using 2 instructions to read any word in the data segment. (example from Hennessy et al. page A-21)

Solution Register $gp (decimal number 28) holds the constant value 0x10008000 This allows us to offset back 32k bytes to the beginning of the data segment. Or offset forward 32k bytes. To load the word stored at 0x10010020 we can use: lw $s1, 0x8020 ($gp)

Offsets in Branch and Jump instructions In load word and store word instructions the 16 bit offset field of instruction counted number of bytes. In branch (16 bit offset field) and jump (26 bit offset field) the offset fields count the number of instructions to offset. Since instructions are 4 bytes.. This is also the number of words to offset…

Time Units How long is a microsecond? How long is a nanosecond? How long is a picosecond? If a clock runs at 450MHZ how long is a clock cycle? If a clock runs at 1.2GHZ how long is clock cycle?

Cycles Per Instruction Different Instructions may take different numbers of clock cycles to execute. CPI (Cycles Per Instruction) refers to number of clock cycles an instruction takes in a design What is average CPI of the following 600 MHZ machine? What is the MIPS rating? Instruction Class CPI Freq Load Word 8 31% Store Word 7 21% ALU (R format) 6 41% Branch 5 5% Jump 2 2%

Registers $s0,$s1,…,$s7 (16 through 23) are “callee saved”. What does this mean? Notes on Stack Pointer: Our stack pointer will always point to the last word in the stack. In the real world, the stack pointer occasionally points to the next free space below the stack.