Guy Lemieux, Mehdi Alimadadi, Samad Sheikhaei, Shahriar Mirabbasi University of British Columbia, Canada Patrick Palmer University of Cambridge, UK SoC Energy Savings = Reduce + Reuse + Recycle

2 SoC Energy Savings: The 3 R’sRe-useEnergy RecycleEnergy ReduceEnergy Today, already a common strategy Tomorrow, we need to do more of this!! How? Case Study of a 660MHz DC-DC Power Converter

3 The Problem Chip design –Fixed throughput goal –High-performance  High power Power reduction –Reduce C –Reduce f  lower throughput  add parallelism  increase C –Reduce f and V  lower throughput  add parallelism  decrease P

4 Solutions 1 Problem Standard CMOS design tricks –Resize transistors for power (not delay) –Reduce signal transitions (switching activity  ) Glitching (non-functional switching) Un-needed functional switching (clock gating, data gating) –Low-V dd  mixed voltage islands –Low-V t  recover performance due to Low-V dd –Multi-V t, multi-V dd  lower leakage, mixed voltage islands

5 Solutions 2 Problem Circuit-level tricks to reduce energy –Pass transistor logic –Adiabatic logic –Supply stacking –Etc…

6 Power Summary Problem Standard solutions –“Bag of tricks” Mantra: Reduce, Reuse, Recycle –Energy reuse and recycling is new! –… a new trick for the bag ? –…or a whole new bag of tricks?

7 Energy Reuse and Recycling Reuse –Charge used in one part of circuit –Moved and re-used to another part of circuit No regulation, eg, LC-resonator Recycling –Charge used in one part of circuit Not all the energy in the charge was needed –Re-regulated and delivered to another part of circuit Captures “unused” energy headroom Delivers to where it can be used Not perpetual motion  conversion losses, limited headroom

8 Energy Reuse and Recycling Recycling –Capture under-utilized charge –Re-regulate, deliver elsewhere Needed technology –On-chip dc-dc converters / voltage regulators Step-up and step-down High efficiency All on-chip Low area Small inductors

9 Switch Mode Power Supply CMOS inverter –Power switches –V gate is PWM with duty cycle D to control output L, C is a low-pass filter –V out = V dd * D (step-down or buck converter)

10 CMOS Switch Mode Power Supplies Large M p, M n transistors for low on-resistance –Large input capacitance on gate terminals –Requires strong transistors to drive grate –Front-end drive chain Series of inverters, tapered in size PWM

11 Fully Integrated Fully Integrated CMOS Power Supplies LC ~ 1/F 2 –Operate at high F  shrink L, C on-chip –High F  high power in front-end drive chain –Front-end drive chain How to its shrink energy use ??? PWM

12 Fully Integrated Fully Integrated CMOS Power Supplies Problem –Front-end drive chain uses too much power (at high F) Solution 1.Reduce – a) separate M p, M n chains, b) low-swing 2.Reuse – stack drive chains for M p, M n 3.Recycle – after stacking drive chain, deliver excess energy to the load in a regulated fashion

13 1. Reduce Energy 1a) Independent M p, M n drive chains, enables ZVS –ZVS: both M p, M n off, inductor charges/drains C x 1b) Apply low-swing V dd Low-swing Low-swing

14 2. Reuse Energy 2) Stack M p, M n drive chains –Low-swing = half-swing –Regulate V dd /2 ?? V dd Low-swing Low-swing V dd /2

15 3. Recycle Energy 3) Excess front-end energy sent to load –M p drive chain ~3x bigger, more energy than M n –Linear regulator: 2 diode drop ~V dd /2 V dd V dd /2

16 Simulated Results Efficiency Boost from Recycling

17 Chip: 660MHz DC-DC Power Converter Reuses & Recycles some of its own Energy approx 1.2 x 2.8 mm 2

18 Chip: Technology Highlights dc-dc buck converter, recycles own energy –180nm CMOS –660MHz to reduce LC area 2.5mm 2 layout area, inductor-dominated –2.2V input, V output, 40-55mA –Simulation No recycling: 28% efficient With recycling: 43% efficient

19 Chip: Schematic

20 Chip: Measured Results Standard error bars: measured from 10 chips

21 Chip: Summary Chip Lessons –High-frequency dc-dc conversion works ! –Gives us confidence simulation results are accurate Chip research – mostly $-limited –Need $$ area for these chip designs Reference design – no energy recycling Modified design – energy recycling High currents & parasitics prevent “sharing” just 1 inductor layout –180nm is wrong technology Need multi-V t transistors Need higher frequency & even smaller inductor 90nm $$, 65nm $$$$

22 90nm Chip: Recycle Back-end Clock Energy Benefits –Shared driver chain –C clk added to SMPS Red path –NMOS drains C clk  wastes charge! Blue path –Delay NMOS turn-on (ZVS)  recycles clock energy! Merge 3GHz clock driver & dc-dc converter

23 90nm Chip: Recycle Back-end Clock Energy High-speed ZVS delay circuit for M n –Delay rising edge of V n Recycles 50% of clock energy (sent to load) [ISSCC 2007]

24 Future Work Need to combine ideas –180nm chip: reduce, reuse, recycle front-end drive chain energy – 90nm chip: recycle back-end clock load energy On-chip regulators lead to power savings –Energy recycling: “free” power supply –On-chip voltages Low-voltage islands Dynamic Voltage and Frequency Scaling Adaptive body bias / dynamic V t adjustment On-chip regulators lead to new ideas –New work: low-power 4GHz clock driver inspired by boost converter

25 Future Work Observation –CMOS logic stores energy in capacitors, then discharges it to GND –This is wasteful Question… –Can we make CMOS more efficient, e.g. by recycling the energy through a dc-dc converter ? A new dynamic logic family that uses inductors to drain precharged output nodes instead of pulldown NMOS ?

Please remember to reduce + reuse + recycle. Thank you.

27 Merging 180nm and 90nm Designs