A Front End and Readout System for PET Overview: –Requirements –Block Diagram –Details William W. Moses Lawrence Berkeley National Laboratory Department of Functional Imaging September 7, 2002 See: W. W. Moses, J. W. Young, K. Baker, et al., “The electronics system for the LBNL positron emission mammography (PEM) camera,” IEEE Trans. Nucl. Sci. NS-48, pp. 632–636, J. W. Young, J. C. Moyers, and M. Lenox, “FPGA based front end electronics for a high resolution PET scanner,” IEEE Trans. Nucl. Sci. NS-47, pp. 1676–1680, 1999.

PET Electronics Requirements High Rates –~1 MHz Single Event Rate / Detector Module (~500 Modules) –~10 MHz Coincidence Rate –Asynchronous Inputs “Coincidence” Data  64 Bit Data from   Coinc. –End Points of Chord– 10 7 –10 8 Possible Chords –Coincidences Identified using Time Stamp on Singles Events (Arrival Time of Each Gamma Compared to Master Clock) “Singles” Data  24 Bit Data from Single 511 keV  –Arrival Time– Energy Qualification –Crystal ID (Position)– Depth of Interaction?

Block Diagram: Front End Module Outputs Processed by Analog Subsection Board Analog Subsection Outputs Processed by Detector Head Interface Output from Detector Head Interface is “Singles Events” PC/104 Provides Communication to Host PC Based on CTI PET Systems Electronics

Analog Subsection Given Analog Signals from 4 PMTs, (1) Generate Digital Data Needed to form (a) “Singles Event Word” or (b) Data Needed for Calibration (2) Send Data to Detector Head Interface

How Does the Analog Subsection Work? Analog ASICDiscretesAltera FPGA & RAM Condition, Digitize, Process

Condition (Module Design #1) Analog ASIC X Y Energy CFD ABCDABCD A B D Analog PMT ASIC Generates Analog: Timing Strobe (CFD) Energy Signal (A+B+C+D) X Signal (B+D-A-C) Y Signal (A+B-C-D) Adjustable: Gains (4), CFD Settings, Shaping Time, Test Pulse Amplitude

Condition (Module Design #2) PD Analog Crystal ID (7 bits) PMT Analog ASIC X Y Energy CFD ABCDABCD PD Analog ASIC Analog PD ASIC Generates: Analog Energy Signal Digital Crystal Address

Digitize Energy, X Ratio, and Y Ratio Energy Signal Digitized with ADC –Fixed voltage used as V ref X and Y Ratios Digitized with ADC –Energy signal used as V ref ADC input ref E X Y V ref ADC input ref ADC input ref X Ratio (X/E) Y Ratio (Y/E) Energy

Digitize Time TDC Digitizes Time (LSB = ns) –Scaler w/ 16 ns clock for MSBs –10 tap delay line (2 ns / tap) w/ latch for LSBs CFD Starts Event Timing Sequence Clock (16 ns) Counter Delay Line (2 ns taps) 16 ns Taps Latch t1t1 t2t2 t3t3 t1t1 t2t2 t3t3 CFD

Process Channel by Channel Gain Correction Channel by Channel Time Correction Compute Crystal Position Performed in Real-Time –256 kB RAM (calibration constants, lookup tables) –Calculations done in FPGA Result is 24-bit “Singles” Word – Arrival Time– Energy Qualification – Crystal ID (Position)– Depth of Interaction? Result is 24-bit “Singles” Word – Arrival Time– Energy Qualification – Crystal ID (Position)– Depth of Interaction?

Detector Head Interface Given “Singles Event Words” from Several Analog Subsections, (1) Multiplex & FIFO Them (2) Pass Them To the Coincidence Processor Distributes Control Signals –Clock Signals –Setup Information Done using FPGAs

Block Diagram: Back End Multiple Detector Heads One Coincidence Processor Fiber Optic Link to Data Acquisition PC PC/104 Loads Set-Up Information into Coincidence Processor Based on CTI PET Systems Electronics

Coincidence Processor Given Lots of “Singles Event Words” from the Detector Head Interfaces, (1) Identify Coincident Pairs (2) Compute “Coincidence Event Word” “Coincidence Event Word” is: –Chord ID (i.e. location of the 2 crystals) Other Information Dropped (after being used to compute the chord): –Time, Depth, Energy Done using FPGAs

How Does Coincidence Processor Work? Collect Singles for Fixed Time (~256 ns) Start with First Single in List Search Later Events for Other Singles Within  t (~10 ns) of Its Time If Match, Compute Chord Address –Only match geometrically valid pairs –Chord computation done by FPGAs Goto Next Single, Loop Until Done Lots of Parallel Processing

Host Computer Easily Programmable –Pentium PRO? –UNIX Workstation? Controls Runs –Type of Run (Real Data or Calibration) –Issues “Start” and “Stop” Commands Supervises Data Storage Supervises (or Performs) Reconstruction Computes Calibration Constants Stores and Loads “Setup” Constants

Photograph of Components Detector Modules Coincidence Processor Flex Board & PD ASIC Analog Subsection Detector Head Interface

Useful for Compton Camera? Analog Subsection: –New “Signal Conditioning” ASIC Needed –New (But Similar) Digitization Electronics –New (But Similar) Processing Firmware Detector Head Interface: –Identical Coincidence Processor & Host PC: –Identical –Already Scaled to 10 8 Coincidence Circuits... Definitely!

Conclusions PET Camera Electronics Consists Of: Analog Subsection Detector Head Interface Coincidence Processor Host Computer High Rate Capability 10 7 Coincident Events per Second (Limited by Detector Dead Time) Good Energy & Timing Resolution Extensive Use of FPGAs (field programmable gate arrays) Very Flexible Algorithms Easily Upgraded & Bugs Fixed New Logic Can Be Loaded In ~1 Second  Eases Testing & Diagnostics