CENG 241 Digital Design 1 Lecture 10 Amirali Baniasadi

2 This Lecture zReview of last lecture: Analysis zChapter 5: State Reduction, Design Procedure

3 zAnalysis: Obtaining a table/diagram for the time sequence of inputs/outputs/internal states. zExamples: State Equations, State Table, State Diagram Analysis of Clocked Sequential Circuits

4 Example of state equation: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A’(t)x(t) A(t+1)=Ax+Bx B(t+1)=A’x y(t)=(A(t)+B(t)).x’(t) = (A+B)x’

5 Example of state tables zPresent state input Next State Output zA B x A B y z z z z z z z z State equation: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A’(t)x(t) y(t)=(A(t)+B(t)).x’(t)

6 Example of state tables-2nd form zPresent state Next State Output z x=0 x=1 x=0 x=1 zAB AB AB y y z z z z State equation: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A’(t)x(t) y(t)=(A(t)+B(t)).x’(t)

7 Example of state diagram Present state Next State Output x=0 x=1 x=0 x=1 AB AB AB y y

8 Mealy & Moore zMealy machine: Output depends on both input & present state zMoore machine: Output only depends on present state.

9 Example of Mealy Machine Present state Next State Output x=0 x=1 x=0 x=1 AB AB AB y y

10 Example of Moore Machine Present state input Next State A B x A B

11 State Reduction and Assignment zGoal: Reduce the number of states while keeping the external input-output requirements. z2 m states need m flip-flops, so reducing the states may reduce flip-flops. zIf two states are equal, one can be removed but what are equal states?

12 State Reduction Example As an example consider the input sequence below: applied and start from state a. State a a b c d e f f g f g a input output

13 State Reduction Example Present State Next State Output x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f g f 0 1 g a f 0 1 States e and g are equal since for each member of the set of inputs, they give the same output and send the circuit either to the same state or an equivalent state.

14 State Reduction Example Present State Next State Output x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f e f 0 1 Table and state diagram after the first reduction: g is removed and replaced by state e. NEW equal states: d and f

15 State Reduction Example Present State Next State Output x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e d 0 1 e a d 0 1 Table and state diagram after the second reduction: f is removed and replaced by state d. If we apply the same sequence State a a b c d e d d e d e a input output

16 Design Procedure First Step: From the word description of the problem derive a state diagram example:design a circuit to detect three or more consecutive 1’s in a string of bits coming through an input line.

17 Design steps z1.From word description, derive state diagram z2.Reduce the number of states z3.Assign binary values to states z4.Obtain the binary coded state table z5.Choose the type of flip-flop used z6.Derive the simplified flip-flop input and output equations z7.Draw the logic diagram zsteps 4 to 7can be implemented by exact algorithms and can be automated. zThe part of the design that is well-defined is referred to as synthesis.

18 State Table for Sequence Decoder zPresent State Input Next State Output zA B x A B y z z z z z z z z A(t+1)= Σ(3,5,7) B(t+1)= Σ(1,5,7) Y(A,B,x)= Σ(6,7)

19 Synthesis Using D Flip-Flops A(t+1)=D A (A,B,x)= Σ(3,5,7) B(t+1)=D B (A,B,x)= Σ(1,5,7) Y(A,B,x)= Σ(6,7)

20 Logic Diagram for a Sequence Detector D A = Ax + Bx D B = Ax + B’x y=AB

21 Excitation Tables zUsing flip-flops other than D can be complicated. zWhy? Input equations for the circuit must be derived indirectly from the state table zExcitation tables can help. zExcitation tables give us the flip-flop input for every state transition. zExample : JK- Recall Q(t+1) = JQ’(t) + K’Q(t) zQ(t) Q(t+1) J K z0 0 0 X z0 1 1 X z1 0 X 1 z1 1 X 0

22 Excitation Tables- T flip-flop zExample : JK- Recall Q(t+1) = TQ’(t) + T’Q(t) = T XOR Q zQ(t) Q(t+1) T z0 0 0 z0 1 1 z1 0 1 z1 1 0

23 Synthesis Using JK Flip-Flops zPresent State Input Next State Flip-Flop Inputs zA B x A B JA KA JB KB z x 0 x z x 1 x z x x 1 z x x 0 z x 0 0 x z x 0 1 x z x 0 x 0 z x 1 x 1 zWe also include J, K input conditions, derived from the excitation table.

24 Synthesis Using JK Flip-Flops

25 Synthesis Using JK Flip-Flops

26 Synthesis Using T Flip-Flops Example: 3-bit Binary Counter The counter counts the clock. Clock does not appear explicitly in the state diagram.

27 Synthesis Using T Flip-Flops Present State Next State Flip-Flop Inputs A2 A1 A0 A2 A1 A0 TA2 TA1 TA

28 Synthesis Using T Flip-Flops

29 Synthesis Using T Flip-Flops

30 Summary zState Reduction, Synthesis