80-Tile Teraflop Network-On- Chip 1

Contents Overview of the chip Architecture ▫Computational Core ▫Mesh Network Router ▫Power save features Performance Evaluation 2

Overview of the chip Purpose: High speed floating point calculations (research chip) Tile based Network- On-Chip Low power consumption 3

4 Computational core The Processing Engine inside the tile

80 GB/s throughput Mesochronous interface Data can be routed across 2 lanes 5 Mesh Network router Overview of the crossbar router

6 Mesh Network router Area reduction trough bit interleaving InterleavingRoutingDe-interleaving

7 Power saving features Sleep transistors: reduce standby leakage Body bias circuits: reduce active leakage Controlled by special instructions Operating voltage: V Operating frequency: 0-5.8GHz

Performance Extreme amount of FLOPS/Watt Low voltage performance still impressive: ▫11W, 310 GFLOPS 8

Evaluation Very scalable Energy efficient Heat spreading possible Fault tolerant Dynamic routing across mesh network 3d stacked memory very promising Not general purpose yet Communication with the outside world is hard Programming might be a problem 9

End of presentation 10