S.Vereschagin, Yu.Zanevsky, F.Levchanovskiy S.Chernenko, G.Cheremukhina, S.Zaporozhets, A.Averyanov R&D FOR TPC MPD/NICA READOUT ELECTRONICS Varna, 2013 Laboratory of High Energy Physics, JINR, Dubna, Russia

CONTENS 1 Introduction (general characteristics of TPC/MPD, & readout electronics requirements) FEE prototype (FEC-64) Main option FEE (FEC-128 & RCU) Conclusions

General view of the MPD detector 2

TPC/MPD 3 12 Readout chambers HV-electrode ~28 KV Field cage beam ~ readout channels E

Main parameters of the TPC 4 Size: 3.4m(length) x 2.8m (diameter); Drift gas: 90% Ar+10% Methane CH4 or 90%Ar+10% CO2; Drift velocity: 5.5 cm/us(Ar + CH4), 2.3 cm/us (Ar + CO2); Length of drift volume: 1.7 m; Data readout: 2x12 sectors (MWPC, cathode pad readout); Maximal event rate 5 kHz; Total number of pads ~ ;

Simulation results 5 Central collision on 9GeV

Main parameters of the FEE TPC 6 Total number of channels ~ Data stream from whole TPC – 5 GB/s Low power consumption – less then 100 mW/ch Fast optical transfer interface Based on ASIC and FPGA

Front-End Electronics prototype 7 FEC-64 channels PASA chip 16 channels ASIC (low noise amplification of the signal) ALTRO chip 16 channels ASIC (digitization and signal processing) FPGA - board control  Signal to noise ratio, S/N - 30   NOISE < 1000e - (С=10-20 pF)  Dynamic Range  Zero suppression  Buffer (4 / 8 events) FTDI USB2.0 (prototype only)

Processing in PASA & ALTRO 8 - FWHM – 190ns - Baseline restoration after 1  s: ~ 5 % in amplifier / shaper ~ 0.1% in dig. chip - FWHM – 190ns - Baseline restoration after 1  s: ~ 5 % in amplifier / shaper ~ 0.1% in dig. chip PASA ALTRO - Baseline corrections - Tail cancellation FWHM ~ 190ns

FEE TESTING 9 FEE on the TPC prototype Pulse after amplification

FEC-64 testing software 10

Block diagram of FEE base 11 RCU Switch 1 FEC 1 FEC 8 FEC 1 FEC 8 Switch 8 Pad Plane ~4500 ch. 128 ch. DAQ PC Slow control Slow control Group 1 Group 8 Trigger

FEE of RoC general diagram 12 RCU FEC group FEC group FEC group FEC group FEC group DAQ PC Ethernet Slow Control system Switch Trigger System Switch 5 Gb/s HLT TPC Optical interface

TPC/MPD READOUT OUTLINE 13 Support high data throughput & maximum parallelization; HLT (TPC), online reconstruction & events compression; Use GPU NVIDIA for computing trigger decision; Like ALICE, ATLAS & CBM experiments;

DATA READOUT 14 PC 1 PC 24 HLT HLT TPC Event builder From other detectors Permanent Data Storage Online reconstruction HLT decision to MPD central trigger processor

Maximum parallelization 15 ROC 1 TPC FEE HLT - TPC GPU BOARD PCI-E 8 Gb/s and more MB-PC ROC 24 TPC FEE PCI-E 1x

Conclusions: 16 Prototype card has been designed 6 prototype cards has been produced & tasted Testing software was developed (LabView & C++) Base FEE concept was developed FEE design toward final version ongoing

I would like to express our gratitude for the help to 17 Victor Chepurnov (JINR) Stepan Razin (JINR) Alexander Moskovsky (JINR) Luciano Musa (CERN)

Thank you for your attention!

Final version of FEE

Basic version of FEC

Switch node

Readout Control Unit

Choice of FPGA technology SRAM, where the programmable switch is controlled by an SRAM memory cell. Flash (or EPROM/EEPROM), where the switch is a floating gate transistor that can be turned off by injecting charge onto the floating gate. Antifuse, where an electrically programmable switch forms a low resistance path between two metal layers.