Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha Reducing jitter utilising adaptive FIR pre-emphasis for high speed serial links Marius Goosen Marius Goosen Saurabh Sinha Saurabh Sinha Microelectronics & Electronics Group University of Pretoria, South Africa Sunday, 25 October 2015

Background M-data lines combined into a high speed serial data line Less skew between lines Higher bandwidth capability Lower pin count and cost of implementation Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha 2

Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha High speed serial links ReferenceData rateTechnologyPre-emphasis [1]1 Gb/sCMOSNone [2]5 Gb/sCMOS3-tap [3]10 Gb/sCMOS5-tap [4]10 Gb/sBiCMOSNone [1] C.Y. Yang and Y. Lee, “A 0.18 μm CMOS 1 Gb/s serial link transceiver by using PWM and PAM techniques”, IEEE International Symp. on Circuits and systems, Vol. 2, pp , Kobe, May [2] C.H. Lin, C.H. Wang and S.J. Jou, “5 Gbps serial link transmitter with pre-emphasis”, IEEE Proc. of the 2003 Asia South Pacific design automation conf., Kitakyushu, pp , Jan [3] M. Li, T. Kwasniewski, S. Wang and Y. Tao, “A 10 Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology”, IEEE Proc. of the 2005 Asia South Pacific design automation conf., Shanghai, pp , Jan [4] D.J. Friedman, M. Meghelli, B.D. Parker, J. Yang, H.A Ainspan, A.V. Rylyakov, Y.H. Kwark, M.B. Ritter, L. Shan, S.J. Zier, M. Soma and M. Soyuer, “SiGe BiCMOS integrated circuits for high speed serial communication links”, IBM J. Res. & Dev., Vol 47, No 2/3, Mar

Frequency dependant distortion: Package parasitics Introduces frequency dependant devices 4 Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha

Frequency dependant distortion: Copper backplane channel Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha 5

Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha Frequency dependant distortion: Channel response Loss of GHz Severe frequency dependent distortion 6

Long tail interferes with adjacent bits Reduced amplitude Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha Frequency dependant distortion: Impulse response 7

Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha Deterministic jitter Deterministic jitter: –Duty cycle distortion –Data dependent jitter DDJ caused by this frequency dependent distortion DDJ causes uncertainty in pulse edges 8 Unit interval Ideal sampling instant Error region

Adaptive pre-emphasis 9 Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha Conventional pre-emphasis –Externally adjustably filter taps –Fixed filter taps Adaptive pre-emphasis –Automatically finds optimal filter taps –Does not require a characterised channel Requires characterised channel

Pilot signaling and peak detection Training sequence together with tap value ensures that a maximum is achieved at the tap of interest 10 Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha

Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha Mathematical simulation results ● Before pre-emphasis: Completely closed eye diagram! 11

Mathematical simulation results ● ● 12 Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha Time (μs) Tap coefficient value Time (μs) Tap coefficient value Time (μs) Tap coefficient value Time (μs) Tap coefficient value

Mathematical simulation results ● ● ● After pre-emphasis tap training: Open eye diagram, minimal jitter. 13 Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha

Mathematical simulation results ● ● ● ● 14 Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha

Mathematical simulation results ● ● ● ● ● 15 Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha ~10 ps ~30 ps ~800 ps

Implemented system 16 Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha

Circuit layouts ● 17 Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha Testability Logic Pilot signal generator FIR filter taps

Circuit layouts ● ● 18 Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha Amplifier + comparatorControl pulse generation

Circuit layouts ● ● ● 19 RX TX Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha

Conclusion DDJ severely distorts the data at the receiver DDJ can be overcome with implementation of pre-emphasis Adaptive pre-emphasis alters for uncharacterised channels Pilot signaling and peak detection: Simple yet effective Awaiting prototype IC sponsored by MOSIS –0.8 mm 2 –21 pins –ETA: March Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase, Elektroniki & Bointšinere bja Khomphutha

Feedback/questions Marius Goosen Carl & Emily Fuchs Institute for Microelectronics Dept.: Electrical, Electronic & Computer Engineering University of Pretoria Pretoria 0002 SOUTH AFRICA Tel: +27-(12) Acknowledgement The authors would like to thank ARMSCOR, the Armaments Corporation of South Africa Ltd, (Act 51 of 2003) for sponsoring this research study.