Circuit Delays. Outline  Calculation of Circuit Delays  Faster Circuits  Look-Ahead Carry Adder.

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Presentation transcript:

Circuit Delays

Outline  Calculation of Circuit Delays  Faster Circuits  Look-Ahead Carry Adder

Outline  Calculation of Circuit Delays  Faster Circuits  Look-Ahead Carry Adder

Calculation of Circuit Delays (1/5)  In general, given a logic gate with delay, t. If inputs are stable at times t 1,t 2,..,t n, respectively; then the earliest time in which the output will be stable is: max(t 1, t 2,.., t n ) + t Logic Gate t1t1 t2t2 tntn :: max (t 1, t 2,..., t n ) + t  To calculate the delays of all outputs of a combinational circuit, repeat above rule for all gates.

Calculation of Circuit Delays (2/5)  As a simple example, consider the full adder circuit where all inputs are available at time 0. (Assume each gate has delay t.) where outputs S and C, experience delays of 2t and 3t, respectively. XYXY S C Z max(0,0)+t = t t max(t,0)+t = 2t max(t,2t)+t = 3t 2t

Calculation of Circuit Delays (3/5)  More complex example: 4-bits parallel adder. C1C1 Y 1 X 1 S1S1 FA C2C2 C5C5 Y 2 X 2 S2S2 FA C3C3 Y 3 X 3 S3S3 FA C4C4 Y 4 X 4 S4S4 FA

Calculation of Circuit Delays (4/5)  Analyse the delay for the repeated block: where X i, Y i are stable at 0t, while C i is assumed to be stable at mt. Full Adder XiYiCiXiYiCi S i C i mt  Performing the delay calculation gives: XiYiXiYi SiSi C i+1 CiCi max(0,0)+t = t t 0 0 mt max(t,mt)+t max(t,mt)+2t max(t,mt)+t

Calculation of Circuit Delays (5/5)  Calculating: When i=1, m=0: S 1 = 2t and C 2 = 3t. When i=2, m=3: S 2 = 4t and C 3 = 5t. When i=3, m=5: S 3 = 6t and C 4 = 7t. When i=4, m=7: S 4 = 8t and C 5 = 9t.  In general, an n-bit ripple-carry parallel adder will experience: S n = ((n-1)*2+2)t C n+1 = ((n-1)*2+3)t as their delay times.  Propagation delay of ripple-carry parallel adders is proportional to the number of bits it handles.  Maximum Delay: ((n-1)*2+3)t

Outline  Calculation of Circuit Delays  Faster Circuits  Look-Ahead Carry Adder

Faster Circuits  Three ways of improving the speed of these circuits: (i) Use better technology (e.g. ECL faster than TTL gates), BUT (a) faster technology is more expensive, needs more power, lower-level of integrations. (b) physical limits (e.g. speed of light, size of atom). (ii) Use gate-level designs to two-level circuits! (use sum- of-products/product-of-sums) BUT (a) complicated designs for large circuits. (b) product/sum terms need MANY inputs! (iii) Use clever look-ahead techniques BUT there are additional costs (hopefully reasonable).

Outline  Calculation of Circuit Delays  Faster Circuits  Look-Ahead Carry Adder

Look-Ahead Carry Adder (1/6)  Consider the full adder: where intermediate signals are labelled as P i, G i, and defined as: P i = X i  Y i G i = X i.Y i  The outputs, C i+1, S i, in terms of P i,G i,C i, are: S i = P i  C i …(1) C i+1 = G i + P i.C i …(2)  If you look at equation (2), G i = X i.Y i is a carry generate signal P i = X i  Y i is a carry propagate signal XiYiXiYi SiSi C i+1 CiCi PiPi GiGi

Look-Ahead Carry Adder (2/6)  For 4-bit ripple-carry adder, the equations to obtain four carry signals are: C i+1 = G i + P i.C i C i+2 = G i+1 + P i+1.C i+1 C i+3 = G i+2 + P i+2.C i+2 C i+4 = G i+3 + P i+3.C i+3  These formulas are deeply nested, as shown here for C i+2 : CiPiCiPi C i+1 GiGi P i+1 G i+1 C i+2 4-level circuit for C i+2 = G i+1 + P i+1.C i+1

Look-Ahead Carry Adder (3/6)  Nested formula/gates cause ripple-carry propagation delay.  Can reduce delay by expanding and flattening the formula for carries. For example, C i+2 C i+2 = G i+1 + P i+1.C i+1 = G i+1 + P i+1.(G i + P i.C i ) = G i+1 + P i+1.G i + P i+1.P i.C i  New faster circuit for C i+2 C i P i P i+1 GiGi G i+1 C i+2

Look-Ahead Carry Adder (4/6)  Other carry signals can also be similarly flattened. C i+3 = G i+2 + P i+2 C i+2 = G i+2 + P i+2 (G i+1 + P i+1 G i + P i+1 P i C i ) = G i+2 + P i+2 G i+1 + P i+2 P i+1 G i + P i+2 P i+1 P i C i C i+4 = G i+3 + P i+3 C i+3 = G i+3 + P i+3 (G i+2 + P i+2 G i+1 + P i+2 P i+1 G i + P i+2 P i+1 P i C i ) = G i+3 + P i+3 G i+2 + P i+3 P i+2 G i+1 + P i+3 P i+2 P i+1 G i + P i+3 P i+2 P i+1 P i C i  Notice that formulae gets longer with higher carries.  Also, all carries are two-level “sum-of-products” expressions, in terms of the generate signals, Gs, the propagate signals, Ps, and the first carry-in, C i.

Look-Ahead Carry Adder (5/6)  We employ the look-ahead formula in this lookahead- carry adder circuit

Look-Ahead Carry Adder (6/6)  The IC chip allows faster lookahead adder to be built.  Maximum propagation delay is 4t (t to get generate and propagate signals, 2t to get the carries and t for the sum signals) where t is the average gate delay.