Chapter 4: Processor Architecture How does the hardware execute the instructions? We’ll see by studying an example system  Based on simple instruction set devised for this purpose  Y86, inspired by x86  Fewer data types, instructions, addressing modes  Simpler encodings  Reasonably complete for integer programs  We’ll design hardware to implement Y86 ISA  Basic building blocks  Sequential implementation  Pipelined implementation

Instruction Set Architecture Defines interface between hardware and software  Software spec is assembly language  State: registers, memory  Instructions, encodings  Hardware must execute instructions correctly  May use variety of transparent tricks to make execution fast.  Results must match sequential execution. ISA is a layer of abstraction  Above: how to program machine  Below: what needs to be built ISA CompilerOS CPU Design Circuit Design Chip Layout Application Program

Y86 Processor and System State  Program Registers  Same 8 as with IA32. Each 32 bits  Condition Codes  Single-bit flags as in x86: OF (Overflow), ZF (Zero), SF (Negative)  Program Counter  Indicates address of instruction  Memory  Byte-addressable storage, words in little-endian byte order  Stat  Indicates exceptional outcomes (bad opcode, bad address, halt) %eax %ecx %edx %ebx %esi %edi %esp %ebp RF: Program registers ZFSFOF CC: Condition codes PC DMEM: Memory Stat: Program Status

Y86 Instructions Format  1 to 6 bytes of information read from memory  Can determine instruction length from first byte  Not as many instruction types, and simpler encoding than IA32  Each accesses and modifies some portion of the CPU and system state  Program registers  Condition codes  Program counter  Memory contents

Encoding Registers Each register has 4-bit ID  Similar encoding used in IA32  But we never deciphered encoding to notice! Register ID 0xF indicates “no register”  Will use this in our hardware design in multiple places  Could otherwise encode register # in 3 bits  Simplifies decoding of instructions %eax %ecx %edx %ebx %esi %edi %esp %ebp

Instruction Example Addition instruction  Add value in register rA to that in register rB  Store result in register rB  Y86 allows addition to be applied to register data only  Set condition codes based on result  Two-byte encoding  First byte indicates instruction type  Second gives source and destination registers  e.g., addl %eax,%esi has encoding addl rA, rB 60 rArB Encoded Representation Generic Form

Arithmetic and Logical Operations  Refer to generically as “ OPl ”  Encodings differ only by “function code”  Low-order 4 bits in first instruction word  All set condition codes as side effect addl rA, rB 60 rArB subl rA, rB 61 rArB andl rA, rB 62 rArB xorl rA, rB 63 rArB Add Subtract (rA from rB) And Exclusive-Or Instruction CodeFunction Code

Move Operations  Similar to the IA32 movl instruction  Simpler format for memory addresses  Separated into different instructions to simplify hardware implementation rrmovl rA, rB 20 rArB Register --> Register Immediate --> Register irmovl V, rB 30F rB V Register --> Memory rmmovl rA, D ( rB) 40 rArB D Memory --> Register mrmovl D ( rB), rA 50 rArB D

Move Instruction Examples irmovl $0xabcd, %edxmovl $0xabcd, %edx30 82 cd ab IA32Y86Encoding rrmovl %esp, %ebxmovl %esp, %ebx20 43 mrmovl -12(%ebp),%ecxmovl -12(%ebp),%ecx50 15 f4 ff ff ff rmmovl %esi,0x41c(%esp)movl %esi,0x41c(%esp) — movl $0xabcd, (%eax) — movl %eax, 12(%eax,%edx) — movl (%ebp,%eax,4),%ecx c

Jump Instructions  Refer to generically as “ jXX ”  Encodings differ only by “function code”  Based on values of condition codes  Same as IA32 counterparts  Encode full destination address  Unlike PC-relative addressing in IA32 jmp Dest 70 Jump Unconditionally Dest jle Dest 71 Jump When Less or Equal Dest jl Dest 72 Jump When Less Dest je Dest 73 Jump When Equal Dest jne Dest 74 Jump When Not Equal Dest jge Dest 75 Jump When Greater or Equal Dest jg Dest 76 Jump When Greater Dest

Stack Operations  Decrement %esp by 4  Store word from rA to memory at %esp  Like IA32  Read word from memory at %esp  Save in rA  Increment %esp by 4  Like IA32 pushl rA a0 rA 8 popl rA b0 rA 8 Same stack conventions as IA32

Subroutine Call and Return  Push address of next instruction onto stack  Start executing instructions at Dest  Like IA32  Pop value from stack  Use as address for next instruction  Like IA32 call Dest 80 Dest ret 90

Miscellaneous Instructions  Don’t do anything  Stop executing instructions  IA32 has comparable instruction, but it can’t be executed in user mode  We will use this instruction to stop the simulator nop 00 halt 10

Y86 Instruction Set Byte pushl rA A0 rA F jXX Dest 7 fn Dest popl rA B0 rA F call Dest 80 Dest rrmovl rA, rB 20 rArB irmovl V, rB 30F rB V rmmovl rA, D ( rB ) 40 rArB D mrmovl D ( rB ), rA 50 rArB D OPl rA, rB 6 fnrArB ret 90 nop 00 halt 10 addl 60 subl 61 andl 62 xorl 63 jmp 70 jle 71 jl 72 je 73 jne 74 jge 75 jg 76

Writing Y86 Code Best to use C compiler as much as possible  Write code in C  Compile for IA32 with gcc -S  Hand translate into Y86 Coding example  Find number of elements in null-terminated list int len1(int a[]); a  3

Y86 Code Generation Example First try  Write typical array code  Compile with gcc -O2 -S Problem  Hard to do array indexing on Y86: no scaled addressing modes /* Find number of elements in null-terminated list */ int len1(int a[]) { int len; for (len = 0; a[len]; len++) ; return len; } L18: incl %eax cmpl $0,(%edx,%eax,4) jne L18 x86 code

Y86 Code Generation Example #2 Second try  Revise to use pointers  Compile with gcc -O2 -S Result  Doesn’t use indexed addressing /* Find number of elements in null-terminated list */ int len2(int a[]) { int len = 0; while (*a++) len++; return len; } L5: movl (%edx),%eax incl %ecx addl $4,%edx testl %eax,%eax jne L5 x86 code

Y86 Code Generation Example #3 IA32 code  Setup Y86 code  Setup len2: pushl %ebp xorl %ecx,%ecx movl %esp,%ebp movl 8(%ebp),%edx movl (%edx),%eax je L7 len2: pushl %ebp# Save %ebp xorl %ecx,%ecx# len = 0 rrmovl %esp,%ebp# Set frame mrmovl 8(%ebp),%edx# Get a mrmovl (%edx),%eax# Get *a je L7# Goto exit Hand translation

Y86 Code Generation Example #4 IA32 code  Loop + Finish Y86 code  Loop + Finish L5: movl (%edx),%eax incl %ecx addl $4,%edx testl %eax,%eax jne L5 movl %ebp,%esp movl %ecx,%eax popl %ebp ret L5: mrmovl (%edx),%eax # Get *a irmovl $1,%esi addl %esi,%ecx# len++ irmovl $4,%esi addl %esi,%edx# a++ andl %eax,%eax# *a == 0? jne L5# No--Loop rrmovl %ebp,%esp# Pop rrmovl %ecx,%eax# Rtn len popl %ebp ret Hand translation

Y86 Program Structure  Programmer must do more work; no compiler, linker, run- time system  Make program placement explicit  Stack initialization must be explicit (addr. 0x100)  Must ensure code is not overwritten!  Must initialize data  Can use symbolic names irmovl Stack,%esp# Set up stack rrmovl %esp,%ebp# Set up frame irmovl List,%edx pushl %edx# Push argument call len2# Call Function halt# Halt.align 4 List:# List of elements.long 5043.long 6125.long 7395.long 0 # Function len2:... # Allocate space for stack.pos 0x100 Stack:

Assembling Y86 Program  Generates “object code” file eg.yo  Actually looks like disassembler output  ASCII file to make it easy for you to read unix> yas eg.ys 0x000: | irmovl Stack,%esp# Set up stack 0x006: 2045 | rrmovl %esp,%ebp# Set up frame 0x008: | irmovl List,%edx 0x00e: a028 | pushl %edx # Push argument 0x010: | call len2 # Call Function 0x015: 10 | halt # Halt 0x018: |.align 4 0x018: | List: # List of elements 0x018: b |.long x01c: ed |.long x020: e31c0000 |.long x024: |.long 0

Simulating Y86 Program  Instruction set simulator  Computes effect of each instruction on processor state  Prints changes in state from original unix> yis eg.yo Stopped in 41 steps at PC = 0x16. Exception 'HLT', CC Z=1 S=0 O=0 Changes to registers: %eax:0x x %ecx:0x x %edx:0x x %esp:0x x000000fc %ebp:0x x %esi:0x x Changes to memory: 0x00f4:0x x x00f8:0x x x00fc:0x x

CISC Instruction Sets CISC: Complex Instruction Set Computer  Dominant style of machines designed prior to ~1980 Stack-oriented instruction set  Use stack to pass arguments, save program counter  Explicit push and pop instructions Arithmetic instructions can access memory  addl %eax, 12(%ebx,%ecx,4)  Requires memory read and write + complex address calculation Condition codes  Set as side effect of arithmetic and logical instructions Philosophy  Add instructions to perform “typical” programming tasks

RISC Instruction Sets Reduced Instruction Set Computer  Early projects at IBM, Stanford (Hennessy), and Berkeley (Patterson) Fewer, simpler instructions in ISA (initially)  Takes more to perform same operations (relative to CISC)  But an instruction can execute faster on simpler hardware Register-oriented instruction set  Many more (typically  32) registers  Used for arguments, return value and address, temporaries Only load and store instructions can access memory  Similar to Y86 mrmovl and rmmovl No condition codes  Test instructions return 0/1 in general purpose register

Example: MIPS Registers

Example: MIPS Instructions OpRaRbOffset OpRaRbRdFn00000 R-R OpRaRbImmediate R-I Load/Store addu $3,$2,$1# Register add: $3 = $2+$1 addu $3,$2,3145# Immediate add: $3 = $ sll $3,$2,2# Shift left: $3 = $2 << 2 lw $3,16($2)# Load Word: $3 = M[$2+16] sw $3,16($2)# Store Word: M[$2+16] = $3 OpRaRbOffset Branch beq $3,$2,dest# Branch when $3 = $2

CISC vs. RISC Debate Strong opinions at the time!  CISC arguments  Easy for compiler (bridge semantic gap)  Concise object code (memory was expensive)  RISC arguments  Simple is better for optimizing compilers  A simple CPU can be made to run very fast Current status  For desktop processors, choice of ISA not a technical issue  With enough hardware, anything can be made to run fast  Code compatibility more important  For embedded processors, RISC makes sense  Smaller, cheaper, less power

4.1 Summary Y86 instruction set architecture  Similar state and instructions as IA32  Simpler encodings  Small instruction set  Y86 somewhere between CISC and RISC  Changes from x86 consistent with RISC principles

4.2: Logic Design: A Brief Review Fundamental hardware requirements  Communication  How to get values from one place to another  Computation  Storage All are simplified by restricting to 0s and 1s  Communication  Low or high voltage on wire  Computation  Compute Boolean functions  Storage  Store bits of information

Communication: Digital Signals  Use voltage thresholds to extract discrete values from continuous signal  Simplest version: 1-bit signal  Either high range (1) or low range (0)  With guard range between them  Not strongly affected by noise or low quality circuit elements  Can make circuits simple, small, and fast Voltage Time 0 1 0

Computation: Logic Gates  Outputs are Boolean functions of inputs  Respond continuously to changes in inputs  After some small delay Voltage Time a b a && b Rising Delay Falling Delay

Combinational Circuits Acyclic network of logic gates  Continuously responds to changes on primary inputs  Primary outputs become (after some delay) Boolean functions of primary inputs Acyclic Network Primary Inputs Primary Outputs

Bit Equality  Generate 1 if a and b are equal Hardware control language (HCL)  Very simple hardware description language  Boolean operations have syntax similar to C logical operations  We’ll use it to describe control logic for processors  Much more convenient than drawing gates  Assumes compiler exists to turn HCL into gate equivalent Bit equal a b eq bool eq = (a&&b)||(!a&&!b) HCL Expression

Word Equality  32-bit word size  HCL representation  Equality operation  Generates Boolean value b 31 Bit equal a 31 eq 31 b 30 Bit equal a 30 eq 30 b1b1 Bit equal a1a1 eq 1 b0b0 Bit equal a0a0 eq 0 Eq = = B A Word-Level Representation bool Eq = (A == B) HCL Representation

Bit-Level Multiplexer  Control signal s  Data signals a and b  Output a when s=1, b when s=0 Bit MUX b s a out bool out = (s&&a)||(!s&&b) HCL Expression

Word Multiplexer  Select input word A or B depending on control signal s  HCL representation  Case expression  Series of test : value pairs  Result value determined by first successful test Word-Level Representation HCL Representation b 31 s a 31 out 31 b 30 a 30 out 30 b0b0 a0a0 out 0 int Out = [ s : A; 1 : B; ]; s B A Out MUX

OF ZF CF OF ZF CF OF ZF CF OF ZF CF Arithmetic Logic Unit  Combinational logic  Continuously responding to inputs  Control signal selects function computed  Corresponding to 4 arithmetic/logical operations in Y86  Also computes values for condition codes ALUALU Y X X + Y 0 ALUALU Y X X - Y 1 ALUALU Y X X & Y 2 ALUALU Y X X ^ Y 3 A B A B A B A B

Edge-Triggered Latch (Flip Flop)  Only in latching mode for brief period  On rising clock edge  Value latched depends on data as clock rises  Output remains stable at all other times Q+ Q– R S D C Data Clock T Trigger C D Q+ Time T

Storage: Registers  Each stores word of data (one byte in above register)  Different from program registers (e.g., %eax)  Collection of edge-triggered latches  Loads input on rising edge of clock IO Clock D C Q+ D C D C D C D C D C D C D C i7i7 i6i6 i5i5 i4i4 i3i3 i2i2 i1i1 i0i0 o7o7 o6o6 o5o5 o4o4 o3o3 o2o2 o1o1 o0o0 Clock Structure

Register Operation  Stores data bits  For most of time acts as barrier between input and output  As clock rises, loads input State = x Rising clock  Output = xInput = y x  State = y Output = y y

State Machine Example  Accumulator circuit  Load or accumulate on each cycle Comb. Logic ALUALU 0 Out MUX 0 1 Clock In Load x0x0 x1x1 x2x2 x3x3 x4x4 x5x5 x0x0 x 0 +x 1 x 0 +x 1 +x 2 x3x3 x 3 +x 4 x 3 +x 4 +x 5 Clock Load In Out

Storage: Random-Access Memory  Stores multiple words of memory  Address input specifies which word to read or write  Register file  Holds values of program registers –%eax, %esp, etc.  Register identifier serves as address –ID 0xF implies no read or write performed  Multiple Ports  Can read and/or write multiple words simultaneously –Each has separate address and data input/output Register file Register file A B W dstW srcA valA srcB valB valW Read portsWrite port Clock

Register File Timing Reading  Like combinational logic  Output data generated based on input address  After some delay Writing  Like register (a few slides ago)  Update only as clock rises Register file Register file A B srcA valA srcB valB y 2 Register file Register file W dstW valW Clock x 2 Rising clock   Register file Register file W dstW valW Clock y 2 x 2 2 x

4.2 Summary Computation  Performed by combinational logic  Computes Boolean functions  Continuously reacts to input changes Storage  Registers  Hold single words  Loaded as clock rises  Random-access memories  Hold multiple words  Multiple read and write ports possible  Read word anytime address input changes  Write word only on rising clock edge