1. 15-447 Computer ArchitectureFall 2008 © Sep 3 rd, 2008 Majd F. Sakr msakr@qatar.cmu.edu www.qatar.cmu.edu/~msakr/15447-f08/ CS-447– Computer Architecture M,W 2:30 - 3:50pm Lecture 6 Instruction Set Architecture

2. 15-447 Computer ArchitectureFall 2008 © Hypothetical Machine Consider the following hypothetical machine: # registers = 16 {R0 to R15}  require 4-bits to address them (24 = 16) # memory locations = 256 {M0 to M255}  require 8-bits to address them (28 = 256)

3. 15-447 Computer ArchitectureFall 2008 © Hypothetical Machine (cont’d) # instructions = 32{Inst0 to Inst31}  require 5-bits to be controlled (2 5 = 32) where Inst15 = Add (instruction # 15) & Inst9 = Load (instruction # 9)

4. 15-447 Computer ArchitectureFall 2008 © Example 1: Add R0, R4, R11 AddR0,R4,R11 ; R0 = R4 + R11 01111000001001011 And to make it simpler to read and use we will use the Hex notation 0F04B And the output of the assembler would simply be the following machine code: 0F04B

5. 15-447 Computer ArchitectureFall 2008 © The instruction In fact, each piece of an instruction can be considered as an individual number, & placing these numbers side by side forms the instruction. OpCode Destination Register 1 Source Register 1 Source Register 2 5 bits4 bits 17-bit Instruction

6. 15-447 Computer ArchitectureFall 2008 © Example 2: Load R13, 127 LoadR13,127 ; R13 = (127) 0100111010111 1111 And in the Hex notation 09D7 F And the output of the assembler would simply be the following machine code: 09D7F

7. 15-447 Computer ArchitectureFall 2008 © The instruction In fact, the instruction format Example: OpCode, Operand, Operand, Operand is fixed only for a specific operation OpCodeRegisterMemory Address 5 bits4 bits8 bits 17-bit Instruction

8. 15-447 Computer ArchitectureFall 2008 © Note °When the OpCode consist of a memory R/W, the operand, Source Register 1 & 2 are combined to form the address field of the instruction. °When the OpCode consist of an immediate instruction, the operand, Source Register 1 & 2 are combined to form the constant whenever that is required.

9. 15-447 Computer ArchitectureFall 2008 © The Instruction °OpCode: basic operation of the instruction °Destination Register: register where the result of the operations will be loaded °Source Register 1 & 2: registers where the data will be operated on

10. 15-447 Computer ArchitectureFall 2008 © Instruction size = data word size As you can see from counting the number of bits, this hypothetical machine instruction takes exactly 17-bits which should be the same size as a data word.

11. 15-447 Computer ArchitectureFall 2008 © Design by Starting with the Instruction Size We would like to design a machine with: Instruction size = 8 bits Instruction number = 8 1.No Operation 2. Add 3. Sub 4. Branch 5. Load 6. Store 7. Increment 8. Decrement 3-bits of the instruction word will be reserved to control the 8 desired instructions xxx

12. 15-447 Computer ArchitectureFall 2008 © So we are left with 5-bits for the operands, With which we can address at most: 32 (= 2 5 ) memory locations 32 (= 2 5 ) registers But if we chose to do so, we will be restricted in the number of operands in the instructions to one Design by Starting with the Instruction Size

13. 15-447 Computer ArchitectureFall 2008 © On the other hand if we wish to have instructions with 2 explicit operands; that is still possible with the 5-bits left. Design by Starting with the Instruction Size xxx How ? ! ?

14. 15-447 Computer ArchitectureFall 2008 © How ? ! ? Using bits 3 with 4 and bits 5 with 6 to address 4 registers. xxx 34567 BitsRegisters addressed# of Registers 3 with 4 R1, R2, R3, R44 5 with 6

15. 15-447 Computer ArchitectureFall 2008 © Results °8 Instructions °2 operands addressing 4 registers with 2-bits each °1 operand of 5-bits addressing 32 memory locations Note: # operands increases # registers decreases

16. 15-447 Computer ArchitectureFall 2008 © Consider this Instruction Set Data processing Data storage Data movement Program flow control Sub000Load010Read100GoTo110 Add001Store011Write101Branch I f111

17. 15-447 Computer ArchitectureFall 2008 © Execution of a simple program The following program was loaded in memory starting from memory location 0. 0000 Load R2, ML4 ; R2 = (ML4) = 5 = 101 2 0001 Read R3, Input14 ; R3 = input device 14 = 7 0010 Sub R1, R3, R2 ; R1 = R3 – R2 = 7 – 5 = 2 0011 Store R1, ML5 ; store (R1) = 2 in ML5

18. 15-447 Computer ArchitectureFall 2008 © The Program in Memory LoadR2,ML4 010100100 ReadR3,Input14 100110100 SubR1,R3,R2 000011110 StoreR1,ML5 011010101 00000 010100110 10001 100110100 20010 000011110 30011 011010111 40100 000000101 …… Don’t care 141011 Input Port 151111 Output Port Address Content

19. 15-447 Computer ArchitectureFall 2008 © I.R. P.C. 010100110 LoadR2, ML4 ; 010100110 Load... R1 R2 R3 000000101 0 CPU 1

20. 15-447 Computer ArchitectureFall 2008 © ReadR3, Input14; 100110100 Read... R1 R2 R3 000000101 CPU 1 2 010100110100110100 000000111

21. 15-447 Computer ArchitectureFall 2008 © SubR1, R3, R2; 000011110 Sub... R1 R2 R3 000000101 CPU 2 3 100110101 000000111000000101 000000010000000111 000011110

22. 15-447 Computer ArchitectureFall 2008 © Store R1, ML5; 011010111 Don’t Care... R1 R2 R3 000000101 CPU 3 4 011010111 Next Instruction 000000010000000111 Store

23. 15-447 Computer ArchitectureFall 2008 © Before Program Execution In the Memory 00000 010100110 10001 100110100 20010 000011110 30011 011010111 40100 000000101 50101Don’t care …… 141011 Input Port 151111 Output Port Address Content 000000010 After Program Execution

24. 15-447 Computer ArchitectureFall 2008 © Instruction Formats °Layout of bits in an instruction °Includes OpCode °Includes (implicit or explicit) operand(s) °Usually more than one instruction format in an instruction set

25. 15-447 Computer ArchitectureFall 2008 © Instruction Length °Affected by and affects: Memory size Memory organization Bus structure CPU complexity CPU speed °Trade off between powerful instruction types and saving space (bits).

26. 15-447 Computer ArchitectureFall 2008 © Allocation of Bits °Number of addressing modes °Number of operands °Register versus memory °Number of registers °Address range °Address granularity

27. 15-447 Computer ArchitectureFall 2008 © Addressing Modes °Immediate °Direct °Indirect °Register °Register Indirect °Displacement (Indexed) °Stack

28. 15-447 Computer ArchitectureFall 2008 © Immediate Addressing °Operand is part of instruction °The address field points to the operand °e.g. ADD 525 Add 525 to contents of accumulator 525 is the operand °No memory reference to fetch data °Fast °Limited range

29. 15-447 Computer ArchitectureFall 2008 © Immediate Addressing Diagram Instruction OpCodeOperand Example: ADD 525 ; AC = AC + 525 In an Accumulator-Based machine, we would like to add 525 to the accumulator, the result will be stored in the accumulator itself.

30. 15-447 Computer ArchitectureFall 2008 © Direct Addressing °Address field contains address of operand °Effective address (EA) = address field A °e.g. ADD A Look in memory at address A for operand Add contents of (A) to accumulator

31. 15-447 Computer ArchitectureFall 2008 © Direct Addressing (cont’d) °Single memory reference to access data °No additional calculations to work out effective address °Limited address space

32. 15-447 Computer ArchitectureFall 2008 © Direct Addressing Diagram Instruction Operand Memory OpCodeOperand Example: ADD (Addr2) ; AC = AC + (2) ; (2) = 255

33. 15-447 Computer ArchitectureFall 2008 © Indirect Addressing (1) °Memory cell pointed to by address field contains the address of (pointer to) the operand °EA = (A) Look in A, find address (A) and look there for operand °e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator

34. 15-447 Computer ArchitectureFall 2008 © Indirect Addressing (2) °Large address space °2 n where n = address word length °May be nested, multilevel, cascaded e.g. EA = ((A)) -Draw the diagram yourself °Multiple memory accesses to find operand °Hence slower

35. 15-447 Computer ArchitectureFall 2008 © Indirect Addressing Diagram Memory Instruction Pointer to Operand Memory Operand OpCodeOperand ADD ((1)) ; AC = AC + ((1)) ((1)) = (3) = 255 = operand

36. 15-447 Computer ArchitectureFall 2008 © Register Addressing (1) °Operand is held in register named in address field °EA = R °Limited number of registers °Very small address field needed Shorter instructions Faster instruction fetch

37. 15-447 Computer ArchitectureFall 2008 © Register Addressing (2) °No memory access °Very fast execution °Very limited address space °Multiple registers helps performance Requires good assembly programming or compiler writing C programming: -register int a;

38. 15-447 Computer ArchitectureFall 2008 © Register Addressing Diagram Instruction Operand Registers OpCodeOperand ADD R3 ; AC = AC + R3 ; AC = AC + 255

39. 15-447 Computer ArchitectureFall 2008 © Register Indirect Addressing °Similar to indirect addressing °EA = (R) °Operand is in memory cell pointed to by contents of register R °Large address space (2 n ) °One fewer memory access than indirect addressing

40. 15-447 Computer ArchitectureFall 2008 © Register Indirect Addressing Diagram Instruction Pointer to Operand OpCodeOperand Memory Operand Example: ADD (R3) ; AC = AC + (R3) = AC + (1) ; AC = AC + 255 Registers

41. 15-447 Computer ArchitectureFall 2008 © Displacement Addressing °EA = A + (R) °Address field hold two values A = base value R = register that holds displacement or vice versa

42. 15-447 Computer ArchitectureFall 2008 © Displacement Addressing Diagram OpCodeRegister RAddress A Instruction Pointer to Operand Registers + Memor y Operand ADD (R2, BaseAddress) ; AC = AC + ; (R2+BaseAddress) ; AC = AC + (1) = AC + 255

43. 15-447 Computer ArchitectureFall 2008 © Relative Addressing °A version of displacement addressing °R = Program counter, PC °EA = A + (PC) °i.e. get operand from A cells from current location pointed to by PC

44. 15-447 Computer ArchitectureFall 2008 © Base-Register Addressing °A holds displacement °R holds pointer to base address °R may be explicit or implicit

45. 15-447 Computer ArchitectureFall 2008 © Indexed Addressing °A = base °R = displacement °EA = A + R °Good for accessing arrays EA = A + R R++

46. 15-447 Computer ArchitectureFall 2008 © Combinations °Postindex °EA = (A) + (R) °Preindex °EA = (A+(R)) °(Draw the diagrams)

47. 15-447 Computer ArchitectureFall 2008 © Stack Addressing °Operand is (implicitly) on top of stack °e.g. ADDPop top two items from stack and add

48. 15-447 Computer ArchitectureFall 2008 © Byte ordering – Big Endian Bytes are ordered left to right (starting at “big end”) Byte 0 at the leftmost (most significant) to byte 3 at the rightmost (least significant) 0123 Word 0 Word 1 Bit 31 Bit 0 Byte 0Byte 1Byte 2Byte 3 Byte 4Byte 5Byte 6Byte 7

49. 15-447 Computer ArchitectureFall 2008 © °Byte 3 at the leftmost (MSB) to byte 0 at the rightmost (LSB) °Bytes are ordered right to left (starting at “little end”) Byte ordering – Little Endian 3210 Word 0 Word 1 Bit 31 Bit 0 Byte 3Byte 2Byte 1Byte 0 Byte 7Byte 6Byte 5Byte 4

50. 15-447 Computer ArchitectureFall 2008 © An Example ISA – IA32

51. 15-447 Computer ArchitectureFall 2008 © Moving Data: IA32 °Moving Data movl Source,Dest: Move 4-byte (“long”) word Lots of these in typical code °Operand Types Immediate: Constant integer data -Like C constant, but prefixed with ‘ $ ’ -E.g., $0x400, $-533 -Encoded with 1, 2, or 4 bytes Register: One of 8 integer registers -But %esp and %ebp reserved for special use -Others have special uses for particular instructions Memory: 4 consecutive bytes of memory -Various “address modes” %eax %edx %ecx %ebx %esi %edi %esp %ebp

52. 15-447 Computer ArchitectureFall 2008 © movl Operand Combinations °Cannot do memory-memory transfer with a single instruction movl Imm Reg Mem Reg Mem Reg Mem Reg SourceDestC Analog movl $0x4,%eaxtemp = 0x4; movl $-147,(%eax)*p = -147; movl %eax,%edxtemp2 = temp1; movl %eax,(%edx)*p = temp; movl (%eax),%edxtemp = *p; Src,Dest

53. 15-447 Computer ArchitectureFall 2008 © Simple Addressing Modes °Normal(R)Mem[Reg[R]] Register R specifies memory address movl (%ecx),%eax °DisplacementD(R)Mem[Reg[R]+D] Register R specifies start of memory region Constant displacement D specifies offset movl 8(%ebp),%edx

54. 15-447 Computer ArchitectureFall 2008 © Indexed Addressing Modes °Most General Form °D(Rb,Ri,S)Mem[Reg[Rb]+S*Reg[Ri]+ D] D: Constant “displacement” 1, 2, or 4 bytes Rb: Base register: Any of 8 integer registers Ri:Index register: Any, except for %esp -Unlikely you’d use %ebp, either S: Scale: 1, 2, 4, or 8 °Special Cases °(Rb,Ri)Mem[Reg[Rb]+Reg[Ri]] °D(Rb,Ri)Mem[Reg[Rb]+Reg[Ri]+D] °(Rb,Ri,S)Mem[Reg[Rb]+S*Reg[Ri]]

55. 15-447 Computer ArchitectureFall 2008 © Address Computation Examples %edx %ecx 0xf000 0x100 ExpressionComputationAddress 0x8(%edx)0xf000 + 0x80xf008 (%edx,%ecx)0xf000 + 0x1000xf100 (%edx,%ecx,4)0xf000 + 4*0x1000xf400 0x80(,%edx,2)2*0xf000 + 0x800x1e080

56. 15-447 Computer ArchitectureFall 2008 © Some Arithmetic Operations FormatComputation °Two Operand Instructions addl Src,DestDest = Dest + Src subl Src,DestDest = Dest - Src imull Src,DestDest = Dest * Src sall Src,DestDest = Dest << SrcAlso called shll sarl Src,DestDest = Dest >> SrcArithmetic shrl Src,DestDest = Dest >> SrcLogical xorl Src,DestDest = Dest ^ Src andl Src,DestDest = Dest & Src orl Src,DestDest = Dest | Src

57. 15-447 Computer ArchitectureFall 2008 © Some Arithmetic Operations FormatComputation °One Operand Instructions incl DestDest = Dest + 1 decl DestDest = Dest - 1 negl DestDest = - Dest notl DestDest = ~ Dest

58. 15-447 Computer ArchitectureFall 2008 © %eax %ecx %edx %ebx %esi %edi %esp %ebp Another Example ISA, Y86 Program Registers -Same 8 as with IA32. Each 32 bits Condition Codes -Single-bit flags set by arithmetic or logical instructions –OF: OverflowZF: ZeroSF:Negative Program Counter -Indicates address of instruction Memory -Byte-addressable storage array -Words stored in little-endian byte order Program registers Condition codes PC Memory OFZFSF

59. 15-447 Computer ArchitectureFall 2008 © Y86 Instructions °Format 1--6 bytes of information read from memory -Can determine instruction length from first byte -Not as many instruction types, and simpler encoding than with IA32 Each accesses and modifies some part(s) of the program state

60. 15-447 Computer ArchitectureFall 2008 © Encoding Registers °Each register has 4-bit ID Same encoding as in IA32 °Register ID 8 indicates “no register” Will use this in our hardware design in multiple places %eax %ecx %edx %ebx %esi %edi %esp %ebp 0 1 2 3 6 7 4 5

61. 15-447 Computer ArchitectureFall 2008 © Instruction Example °Addition Instruction Add value in register rA to that in register rB -Store result in register rB -Note that Y86 only allows addition to be applied to register data Set condition codes based on result e.g., addl %eax,%esi Encoding: 60 06 Two-byte encoding -First indicates instruction type -Second gives source and destination registers addl rA, rB 60 rArB Encoded Representation Generic Form

62. 15-447 Computer ArchitectureFall 2008 © Arithmetic and Logical Operations Refer to generically as “ OPl ” Encodings differ only by “function code” -Low-order 4 bytes in first instruction word Set condition codes as side effect addl rA, rB 60 rArB subl rA, rB 61 rArB andl rA, rB 62 rArB xorl rA, rB 63 rArB Add Subtract (rA from rB) And Exclusive-Or Instruction CodeFunction Code

63. 15-447 Computer ArchitectureFall 2008 © Move Operations Like the IA32 movl instruction Simpler format for memory addresses Give different names to keep them distinct rrmovl rA, rB 20 rArB Register --> Register Immediate --> Register irmovl V, rB 308 rB V Register --> Memory rmmovl rA, D ( rB) 40 rA rB D Memory --> Register mrmovl D ( rB), rA 50 rA rB D

64. 15-447 Computer ArchitectureFall 2008 © Jump Instructions Refer to generically as “ jXX ” Encodings differ only by “function code” Based on values of condition codes Same as IA32 counterparts Encode full destination address -Unlike PC-relative addressing seen in IA32 jmp Dest 70 Jump Unconditionally Dest jle Dest 71 Jump When Less or Equal Dest jl Dest 72 Jump When Less Dest je Dest 73 Jump When Equal Dest jne Dest 74 Jump When Not Equal Dest jge Dest 75 Jump When Greater or Equal Dest jg Dest 76 Jump When Greater Dest

65. 15-447 Computer ArchitectureFall 2008 © Stack Operations Decrement %esp by 4 Store word from rA to memory at %esp Like IA32 Read word from memory at %esp Save in rA Increment %esp by 4 Like IA32 pushl rA a0 rA 8 popl rA b0 rA 8

66. 15-447 Computer ArchitectureFall 2008 © Subroutine Call and Return Push address of next instruction onto stack Start executing instructions at Dest Like IA32 Pop value from stack Use as address for next instruction Like IA32 call Dest 80 Dest ret 90

67. 15-447 Computer ArchitectureFall 2008 © Miscellaneous Instructions Don’t do anything Stop executing instructions IA32 has comparable instruction, but can’t execute it in user mode We will use it to stop the simulator nop 00 halt 10