Time-Memory Scheduling and Code Generation of Real-Time Embedded Software Chuen-Hau Gau and Pao-Ann Hsiung National Chung Cheng University Chiayi, Taiwan, R.O.C. 8th International Conference on Real-Time Computing Systems and Applications, March 18-20, 2002, Tokyo, Japan

National Chung Cheng University, Taiwan 2 Outline Introduction Previous Work Real-Time Embedded Software Synthesis ATM VPN Server Example Conclusions

National Chung Cheng University, Taiwan 3 Introduction Embedded systems abound in human daily life We interact with embedded systems in our homes, at offices, at labs, on transportations, in communications, … Due to this interaction with humans, most embedded systems are also REAL-TIME systems And, software accounts for more than 70% functionalities in a real-time embedded system

National Chung Cheng University, Taiwan 4 What is an embedded system? Installed in a larger system Dedicated task Small Memory Space (200~400 KB) Low Processing Power (100~200 MHz ) Unstable Environment (mobile, …) Reactive Real-Time

National Chung Cheng University, Taiwan 5 Embedded System Examples medical instruments home appliances office equipments space crafts research lab equipments factory automation

National Chung Cheng University, Taiwan 6 Embedded System Architecture

National Chung Cheng University, Taiwan 7 Design Issues and Solution 2. Real-Time Constraints 1. Bounded Memory Execution Proposed Solution Time Memory Scheduling (TMS) Code Generation

National Chung Cheng University, Taiwan 8 Previous Work Formal Software Synthesis Safe Petri-Nets (PN)  Quasi-Static Scheduling (QSS) [Lin: DATE’98, DAC’98] Free-Choice PN  Net Decomposition + QSS [Sgroi: DAC’99] Codesign FSM  POLIS [Balarin: ICCD’99] Non-timed multi-rate PN  Reachability graph [Cortadella et al: DAC’00] Time Free-Choice PN  QSS + RTS or FIBS [Hsiung: CODES’01, FORTE’01]

National Chung Cheng University, Taiwan 9 Real-Time Embedded Software (RTES) Model Real-Time Embedded Software is specified as a set of Colored Time Petri Nets (CTPN) Allows explicit modeling of Timing Constraints Memory Usages No free-choice restriction! Larger domain of real-time embedded applications!

National Chung Cheng University, Taiwan 10 Colored Time Petri Nets

National Chung Cheng University, Taiwan 11 Colored Time Petri Nets A CTPN is a 6-tuple (P,T, C, ,M 0,  ) such that: P is a finite set of places, T is a finite set of transitions, P  T  , P  T = , C is a set of colors associated with each token  : (P  T )  (T  P )  2 N  C, a set of weighted arcs such that each arc is associated with a set of integer-color pairs, M 0 : P  2 N  C, the initial marking,  (t ) = ( ,  ), t  T,  : Earliest Firing Time,  : Latest Firing Time.

National Chung Cheng University, Taiwan 12 CTPN Marking A marking is a vector M = where NC i is a set of integer-color pairs representing the non-negative number of colored tokens in place p i. 2 attributes are associated with each M: (1) a time-stamp  (M) (2) a memory-usage  (M)

National Chung Cheng University, Taiwan 13 Valid Firing (System Execution) A transition t is said to be enabled at time  in a marking M with time-stamp  (M) if: (1)  (p k, t)  NC k,   (p k, t) , k  {1, …,|P|}, (2)    (M)    (t) The firing of a transition t at time  in a marking M with time-stamp  (M) is called a valid firing if: Transition Deadline:   (t)    (M)    (t) Memory Constraint:  (M')   max where M' is the marking obtained by firing t in M and  max is the maximum amount of memory available.

National Chung Cheng University, Taiwan 14 RTES Synthesis Problem Target Problem Real-Time Embedded Software Synthesis Given: a set of CTPN S = {A i | i = 1,2,…,n}, an upper-bound  max on memory space, and a set of real-time constraints: CTPN periods, deadlines software code is to be generated such that 1. it can be executed on a single processor, 2. it uses memory less than or equal to  max, and 3. it satisfies all EFT, LFT, and real-time constraints.

National Chung Cheng University, Taiwan 15 RTES Synthesis Algorithm Choice Set: H = {t 2, t 3, t 4 }

National Chung Cheng University, Taiwan 16 RTES Synthesis Algorithm Exclusion Set H = {t 2, t 3, t 4 } Merging of all non-disjoint choice sets

National Chung Cheng University, Taiwan 17 RTES Synthesis Algorithm Time-Memory Scheduling A schedule (sequence of firing transitions) is valid if the following are satisfied: Transition deadline CTPN deadline Memory bound Incomplete exclusion sets are deleted (because corresponding code will be illegal)

National Chung Cheng University, Taiwan 18 RTES Synthesis Algorithm Transition Deadline Satisfaction Assume transition t:  enabled at marking M with time-stamp  (M)  fired at marking M with time-stamp  (M), then it must satisfy  (M) -  (M) +   (t)    (t) transition deadline transition execution time token age

National Chung Cheng University, Taiwan 19 RTES Synthesis Algorithm CTPN Deadline Satisfaction Assume transition t:  fired at marking M  (M) +   (t)  d CTPN deadline for current task transition execution time

National Chung Cheng University, Taiwan 20 RTES Synthesis Algorithm Memory Bound Satisfaction Assume transition t:  fires and CTPN reaches marking M   (M  )   max memory bound memory usage

National Chung Cheng University, Taiwan 21 RTES Synthesis Algorithm while( |Tree| != 0 ) {if( Entire Tree Marked ) CodeGen(); if( Current Node Is Spawned ) {Current Node :: Delete Incomplete Exsets if Current Node :: Has Marked Child Current Node :: Delete Other Child, Mark, Go Parent if(Child := SELECT() == null) Current Node :: Delete Current and Go Parent else Current Node :: Go Child} else {if(Current Node Is A CompleteSchedule) Current Node :: Mark and Go Parent else Current Node :: Spawn} }

National Chung Cheng University, Taiwan 22 RTES Synthesis Algorithm Memory Estimation Global Memory:  G (R), R: tree Local Memory: max t  M (  L (t)), t: transition, M: marking Buffer Memory: Total Memory:

National Chung Cheng University, Taiwan 23 Code Generation A real-time process for each independent task, i.e., each reachability tree # tasks is minimal (= # independent tasks) Main Program Process i Task 1Task 2Task k … Source Transitions in TFCPN

National Chung Cheng University, Taiwan 24 Code Generation Algorithm Extract( CNode ) { if( CNode is leaf ) // no child {Code += getCode(CNode); Code += “return;”; } else if( CNode is branching ) // multi-child {Code += getBranchCode(CNode); for each child node CNode.ci Extract(CNode.ci); } else // one child {Code += getCode(CNode); Extract(CNode.child) } return(Code); }

National Chung Cheng University, Taiwan 25 ATM VPN Server ATM switching nodes interconnect LANs via an ATM backbone. An ATM server: temporarily stores input cells from VCCs (Virtual Channel Connections), and forward VCC cells to the VPCs (Virtual Path Connections) by identifying cell headers.

National Chung Cheng University, Taiwan 26

National Chung Cheng University, Taiwan 27 Functionalities of ATM VPN 1. Message Selective Discarding (MSD): A message discarding technique that avoids buffer overflow by discarding selected incoming cells 2. Weighted Fair Queuing (WFQ): A bandwidth control policy for outgoing flows Thus, there are TWO independent tasks!

National Chung Cheng University, Taiwan 28 ATM VPN Server Message Selective Discarding Cell ExtractCounter WFQ scheduling VCC cell TICK PUSH INSERT POP

National Chung Cheng University, Taiwan 29 CTPN model of MSD in ATM

National Chung Cheng University, Taiwan 30 CTPN models of WFQ, Extract *SCHEDULE_ WFQ READ_BW READ_LAST t13 t14 t15 LAST + BW > GLOBAL_TIME ? N Yp25 p26 p27 p28 p29 P30 INSERT_CELL p34 p35 p33 p32p31 p37 p36 p38 p39 POP CHECK_ QLENGTH t19 COMPUTE_ OUT_TIME *SCHEDULE_ WFQ t17 t18 TICK I=I+1 I=0 t16 READ_SORTER Qlength=0? Y N CELL_OUT_TIME <= GLOBAL_TIME? Y N I=N? N Y

National Chung Cheng University, Taiwan 31 Reachability Tree for MSD Schedule Results: 49 markings 14 schedules 66 instructions 12 Kbytes Memory

National Chung Cheng University, Taiwan 32 Reachability Trees for WFQ and Extract Schedule Results: WFQ 9 markings 2 schedules Extract 13 markings 4 schedules

National Chung Cheng University, Taiwan 33 Scheduling Results Both MSD and Extract call WFQ (2 schedules) MSD Task # schedules = 14  2 = 28 Extract Task # schedules = 4 x 2 = 8

National Chung Cheng University, Taiwan 34 Conclusions A synthesis method for real-time embedded software was presented No free-choice restriction on model Explicit time and data modeling Both real-time constraints and memory constraints are considered for scheduling Minimal number of tasks in generated code Can be used for prototyping platforms