PHENIX upgrade DAQ Status/ HBD FEM experience (so far) The thoughts on the PHENIX DAQ upgrade –Slow download HBD test experience so far –GTM –FEM readout (DCM)

Ethernet in PHENIX Upgrades For the next generation of PHENIX FEM’s, Steve Boose has been working on selecting an Ethernet based controller; same basic features as GAB, but additional capabilities possible, like an additional slow path for reading data Desirable features: –Small footprint, low profile (to fit in VME slot spacing 0.7 in) –Enough CPU and memory to handle ethernet traffic and control –Comfortable development environment –“Open” design so that schematics can be dropped into designs Some disadvantages: –Fatter cable; connectors probably have to be bigger RJ45 –More software complexity –Point-to-point wiring and hubs necessary Current best idea is Freescale’s Motorola Coldfire 5282 board –Schematic freely published; free binary monitor (RTXC) –Linux inside: –About $300 CML-5282 Motorola Coldfire development board (3.5”x4”) (

Updated HBD FEM Diagram Clock Master Clock fanoutADC Optical out Backplane Crate GTM/Ethernet New Daughter card + DCM Test pulse (7 blank boards, 4 crates+ 1 spare+ 2 test stands) (4 blank boards, 1 needed + 1 spare+ 2 test stands) (25 blank boards. We have major of the parts for 5 boards) Optical out – Design is done -- checking New DCM daughter card design is done -- checkinh For Clockmaster, clock fanout, ADC and backplane, the prototype boards are assembled

Clock Master Board GTM Input Clock Circuits Freescale Coldfire Evaluation board Serial data In/out About Freescale coldfire evaluation board: 1)40 MHz system clock – worry about trace length to FPGA 1)Data/clock/address – looks ok on scope 2)Come with TCP/IP software 1)So far --- Low performance 2)Commercial software – expensive Analog Device Blackfin processor has similar device -- it has a system core group Support uclinux + tcp/ip software

GTM interface GTM optical interface provides –4x beam clock  via recover link clock RHIC beam clock depend on collision species –L0 timing, L1 trigger In the GLINK data word New optical protocol (8b/10b encoding) requires reference clock on the receiver end within 100ppm of the transmitter clock. – it is not practical to transfer the clock using the new optical protocol For the upgrade program, we will stay with old GTM interface. –We may have a revised version of current GTM but using the old optical protocol.

Zero suppression daughter card DSP Zero suppression daughter card DSP Zero suppression daughter card DSP Zero suppression daughter card DSP 40 MHz 32 bits DSP Zero suppression daughter card DSP Zero suppression daughter card DSP Zero suppression daughter card DSP Zero suppression daughter card DSP 40 MHz 32 bits DSP Partition Module First Generation DCM Data from FEM FEM can hold up to 5 L1 events The DCM performs zero suppression, data formatting, multiple event buffer, generating “BUSY”, and error checking. DCM has to provide 5 L1 event buffer for FEM First Stage of the event building Average zero suppression factor is ~ 40 for Au-Au mini-bias We have roughly 200 DCM modules 23 DCM crates. 32 bits 40 MHz

New DCM Daughter Card Optical Transceiver Data Flow 80 MHz optical clock reference Altera Stratix GX FPGA (de-serializer, zero suppression, buffer etc) Before the new DCM exist, this new DCM daughter card can use to read out new detectors FEM with old DCM Module. 8b/10b encoding on the optics data stream 16 bits raw data Fix 1.6 Gbits data link