Thermal-aware Steiner Routing for 3D Stacked ICs M. Pathak and S.K. Lim Georgia Institute of Technology ICCAD 07

Outline Introduction Problem formulation 3D Steiner tree construction Thermal-aware through via relocation Experimental results Conclusion

Introduction 3D die stacking technology enables the integration of multiple planar IC in the vertical direction with high-density interconnect through-silicon-vias. One of the major concerns of 3D ICs is thermal dissipation. Effective placement of through vias can play a significant role in lowering the temperature of the chip since these vias establish thermal paths to the heat sink.

Introduction An approach which tries to optimize the location of through vias such that both performance and thermal issues are addressed is important.

Problem Formulation Given: (i) a set of m nets{n 0, n 1, …, n m-1 }, where each net is represented by a list of pins n i ={p 0, p 1,…, p k-1 } with p 0 as the driver. (ii) a 3D routing grid G. (iii) each x/y grid edge is associated with horizontal/vertical wire capacity and z with via capacity. (iv) the location of each pin p(x,y,z). (v) a 3D thermal grid Z with temperature at all grid nodes.

Problem Formulation Goal: Generate a 3D Steiner tree for each net while satisfying the capacity constraints in G. The objective is to minimize: (i) the maximum temperature among all nodes in the thermal grid. (ii) the maximum Elmore delay among all pins in each tree, where the delay is computed based on the given thermal distribution.

Problem Formulation The line resistance per unit length can be calculated as: r(x)=r 0 (1+βT(x)) r 0 : the resistance at 0 ℃ β: the temperature co-efficient of resistance. T(x): the temperature at location x.

Overview of the Approach Two steps: 1) Construction step: perform thermal analysis from the 3D placement. Then, construct a routing tree for each net under the non-uniform thermal profile. 2) Refinement step: optimize the thermal objective by relocating through vias in each tree under given timing constraints.

3D Steiner Tree Construction The basic approach is similar to SERT, where an existing tree is incrementally grown by connecting a new sink pin to it. Start with the driver pin and select the sink pin that minimizes Elmore delay when connected to the tree that is being grown. The goal is to minimize the maximum Elmore delay among all sink pins of the tree.

Overview of the Algorithm

Connection Point and Via Location Edge e(p,c) lies on die 1 with interconnect parasitics r 1 and c 1, whereas a lies on die 2 with r 2 and c 2. d is the point on e(p,c) that is of the shortest distance to a. x is the location of connection point on e(p,c). y is the location of the through via inserted on e(x,a). e(q,b) is another branch in T.

Connection Point and Via Location Compute the Elmore delay change on all sink pins in T caused by adding a to T. δ x : the distance between node p and x. δ q, δ a, δ b, δ c and δ d are used similarly. δ y : the distance between x and y. δ z : the distance between y and a.

Connection Point and Via Location Four case: Case 1: the delay at node a. d(a)=f1+f2+f3+f4.

Connection Point and Via Location Case 2: the new delay at node c: d(c)=f1+f2+f3’+f4’. Case 3: the new delay at node b: d(b)=f1+f2’’+f3’’.

Connection Point and Via Location Case 4: for all other nodes not in Tp, the added delay is a function of the added capacitance.

Thermal-aware Through Via Relocation Movable Range Each via is associated with the movable range, R via, that denotes the range of new location along its route to the connection point so that the timing constraints are not violated. Find a new location for each movable via in each Steiner tree so that the maximum temperature among all nodes is minimized while the timing constraints are not violated.

Fast Thermal Analysis In 3D ICs, the heat sinks are attached to the bottom or top side of the 3D IC stack. The dominant heat flow is in the vertical direction. Do not consider effects of lateral thermal dissipation.

Non-linear Programming

Integer Linear Programming Replace Eq(2) and (3) with:

Experimental Results The v-bound shows the lower bound of the through via usage for each circuit.

Experimental Results Temperature comparison. T org and T opt denote the temperature before and after thermal optimization.

Conclusion This paper presented the first work on the thermal- aware Steiner routing for 3D stacked ICs. 3D Steiner tree construction and through via relocation. The formulation can handle large number of vias simultaneously for an effective temperature optimization.