XFEL C+C HARDWARE : REQUIREMENTS 1) To receive, process and store Timing Signals from TR ( Timing Receiver ) in same crate : - 5 MHz Bunch CLOCK - Bunch.

Slides:



Advertisements
Similar presentations
TDC130: High performance Time to Digital Converter in 130 nm
Advertisements

Clock and Control Status Matt Warren, on behalf of Martin Postranecky.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 4 December 2008 Martin Postranecky Matt Warren, Matthew Wing.
Μ TCA Crate Timing Receiver Crate Processor 100 MHz Clock Start/Info/Stop Bunch Veto FEE Status C+C Master FEE C+C Fanout Slave FEE 5MHz Clock Trigger.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 22 October 2009 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, MANNHEIM 02 July 2009 Martin Postranecky, Matt Warren, Matthew Wing.
4x4 4 8x LVDS on HDMI ( 8x LVDS on SMA ? ) 8x LVDS on HDMI LVDS on SMA LVTTL on Lemo NIM on Lemo LVDS on SMA 4x LVDS on SMA 4x NIM on Lemo 2x NIM on Lemo.
XFEL 2D Pixel Clock and Control System. 2 OUTLINE June meeting at DESY June meeting at DESY C&C Hardware structure C&C Hardware structure C&C Firmware.
XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.
Thoughts on C&C hardware modularity. Concept Master and Slave will be proper AMC AMC boards will be fairly smart: Micro-controller Small FPGA? –So no.
XFEL Meeting, DESY 5 May 2011 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.
XFEL Meeting, RAL 20 January 2011 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.
FF - TB May 10th, L1 L0 FANOUT LOGIC ALICE general Trigger layout FEE LTU CTP L0 BUSY FEE L1 TTC vi VME BUS L2a, L2r L0 TTC ex CH A CH B L2a, L2r.
HEP UCL Cambridge University Imperial College London University of Manchester Royal Holloway, University of London University College London Matthew Warren,
New Corporate Identity Poster Design Department of Physics and Astronomy, University College London Erdem Motuk, Martin Postranecky, Matthew Warren, Matthew.
Clock & Control Card Status 31 March 2009 Martin Postranecky / Matt Warren.
1  1998 Morgan Kaufmann Publishers Interfacing Processors and Peripherals.
01/11/2002SNS Software Final Design Review1 V123S Event Link Encoder, Transmission System and PLL Receiver Thomas M. Kerner (BNL) SNS Global Controls.
Dr. Rabie A. Ramadan Al-Azhar University Lecture 3
ALICE Trigger System Features Overall layout Central Trigger Processor Local Trigger Unit Software Current status On behalf of ALICE collaboration:D. Evans,
Trigger System Functions Master/Slave Operation –Located in Readout Boards’ BE-FPGA, but only active as Master in one slot. –Master controls asynchronous.
20 Feb 2002Readout electronics1 Status of the readout design Paul Dauncey Imperial College Outline: Basic concept Features of proposal VFE interface issues.
RPC Electronics Status Overall system TDC –Digitizing frequency issue (determine the bin size of the TDC value) Discriminator test result Trigger module.
July 10, 2008 PHENIX RPC review C.Y. Chi 1 RPC Front End Electronics On chamber discriminator  The strips  The CMS discriminator chips  The discriminator.
Ionization Profile Monitor Front End (IFE) System Presenter: Kwame Bowie PPD/EED Phone: (630)
7-1 Digital Serial Input/Output Two basic approaches  Synchronous shared common clock signal all devices synchronised with the shared clock signal data.
The TIMING System … …as used in the PS accelerators.
SNS Integrated Control System EPICS Collaboration Meeting SNS Machine Protection System SNS Timing System Coles Sibley xxxx/vlb.
LHC Beam Dump System Technical Audit Trigger Synchronisation Unit.
TID and TS J. William Gu Data Acquisition 1.Trigger distribution scheme 2.TID development 3.TID in test setup 4.TS development.
Trigger Supervisor (TS) J. William Gu Data Acquisition Group 1.TS position in the system 2.First prototype TS 3.TS functions 4.TS test status.
The GANDALF Multi-Channel Time-to-Digital Converter (TDC)  GANDALF module  TDC concepts  TDC implementation in the FPGA  measurements.
SNS Integrated Control System SNS Timing Master LA-UR Eric Bjorklund.
Distribution of machine parameters over GMT in the PS, SPS and future machines J. Serrano, AB-CO-HT TC 6 December 2006.
K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 1 Development of fast electronics for the GRAPES-3 experiment at Ooty K.C. RAVINDRAN On Behalf of GRAPES-3 Collaboration.
Some features of V1495 Shiuan-Hal,Shiu Everything in this document is not final decision!
HBD FEM the block diagram preamp – FEM cable Status Stuffs need to be decided….
11 October 2002Matthew Warren - Trigger Board CDR1 Trigger Board CDR Matthew Warren University College London 11 October 2002.
11th March 2008AIDA FEE Report1 AIDA Front end electronics Report February 2008.
HBD FEM Overall block diagram Individual building blocks Outlook ¼ detector build.
2 4 Dec 2008C+C Crate Layout CC Master TCLKA TCLKB RX17 TX17 RX18 TX18 RX19 TX19 RX20 TX20 (wired-OR) Bunch Clock FE Clock (99MHz) Trig (Start) EncClock.
Local Trigger Unit for NA62 Marián Krivda 1), Cristina Lazzeroni 1), Vlado Černý 2), Tomáš Blažek 2), Roman Lietava 1)2) 1) University of Birmingham, UK.
SNS Integrated Control System Timing Clients at SNS DH Thompson Epics Spring 2003.
C. Combaret DIF_GDIF_MDIF_D ASU 6x 24 HR2 ASU USB Hub RPi USB2 DCC SDCC RPi USB 1 hub+Rpi for 4 cassettes 1 DCC for 8 cassettes (1 spare) Trigger.
Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout.
Leo Greiner PIXEL Hardware meeting HFT PIXEL detector LVDS Data Path Testing.
Timing Requirements for Spallation Neutron Sources Timing system clock synchronized to the storage ring’s revolution frequency. –LANSCE: MHz.
Acquisition Crate Design BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’ 26 August
FPGA firmware of DC5 FEE. Outline List of issue Data loss issue Command error issue (DCM to FEM) Command lost issue (PC with USB connection to GANDALF)
Front-End Electronics for PHENIX Time Expansion Chamber W.C. Chang Academia Sinica, Taipei 11529,Taiwan A. Franz, J. Fried, J. Gannon, J. Harder, A. Kandasamy,
Connector Differential Receiver 8 Channels 65 MHz 12 bits ADC FPGA Receive/buffer ADC data Format triggered Events Generate L1 Primitives Receive timing.
XFEL In-kind Review Committee Meeting, 11 May 2009 Parliament British Museum XFEL clock and control system In kind contribution proposal Development and.
ATLAS SCT/Pixel TIM FDR/PRR28 June 2004 TIM Requirements - John Lane1 ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004 Physics & Astronomy HEP Electronics John.
Electronics Workshop GlueX Collaboration Meeting 28 March 2007 Fast Electronics R. Chris Cuevas Group Leader Jefferson Lab Physics Division Topics: Review.
1 Timing of the calorimeter monitoring signals 1.Introduction 2.LED trigger signal timing * propagation delay of the broadcast calibration command * calibration.
Backplanes for Analog Modular Cameras EVO meeting. March 14 th,
The Clock Distribution inside the CTA Camera Axel Kretzschmann, DESY Zeuthen,
AHCAL Beam Interface (BIF)
ATLAS Local Trigger Processor
Fill-pattern Control System for KEKB
Master I/O Connectors PL12 PL14 PL21 PL20 PL17.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,
Clock & Control Timing and Link 29 July 2008 Matt Warren Maurice Goodrick, Bart Hommels, Marc Kelly, ABSTRACT: A data acquisition system is described.
Timing and Event System S. Allison, M. Browne, B. Dalesio, J
Digitally subtracted pulse between
Clock & Control Timing and Link 29 July 2008 Matt Warren Maurice Goodrick, Bart Hommels, Marc Kelly, ABSTRACT: A data acquisition system is described.
Presentation transcript:

XFEL C+C HARDWARE : REQUIREMENTS 1) To receive, process and store Timing Signals from TR ( Timing Receiver ) in same crate : - 5 MHz Bunch CLOCK - Bunch train TRIGGER - Event Number = TRAIN ID - BUNCH PATTERN or Bunch PATTERN ID 2) To receive BUNCH VETO from Veto Hardware 3) To receive STATUS / ERROR ( and possibly Busy ?? ) from each FEE 4) To distribute to each FEE three fast lines : MHz un-interrupted clock, phase-locked to 5 MHz Bunch Clock - START pulse, followed by TRAIN ID, followed by PATTERN ID, followed by STOP signal - BUNCH VETO signal 5) To process any BUSY information from crate controller to stop the following START pulse 6) To generate all Timing Signals in Stand-Alone mode without TR 7) To synchronise to other light sources Timing Systems, i.e. to accept external CLOCK and possibly TRIGGER at different frequencies 8) To provide diagnostic and visual indication of CLOCK, TRIGGER, etc. performance and presence / absence of any FEE

t1 T1 T2 T1+T2 5 MHz clock in TRIGGER in 100 MHz clock out TRIGGER out VETO out INPUTS AND OUTPUTS – TIMING RELATIONSHIP D2 D1 VETO in

XFEL C+C HARDWARE : MORE INFORMATION / QUESTIONS -1- 1) TRIGGER Telegram from TR : - same line / different lines for TRIGGER, Train ID, Bunch Pattern ?? - Bunch Pattern or Pattern ID ? ( Pattern ID look-up table on C+C ?? ) 2) FEE feedback line : Status only ( e.g.. Normally floating high, pulled low by FEE when powered ), or will contain information ( e.g.. go high when busy or error ) ?? 3) External clock input at other test sites : - 20 MHz range ?? - Always use internal 100 MHz clock or PLL to different clock ?? 4) Bunch Veto signal – how fast / latency ?? 5) Calibration Pattern ?? ( pre-loaded into a memory on C+C ?? ) 6) Veto Disable Pattern ?? 7) 100 MHz clock output : - max. jitter ?? - programmable delay / step size ?? 8) Output Clock / Start/Stop pulses phase relationship : - only adjustable on C+C Master, i.e. same for all FEEs ?? - same cable length for all FEEs ?? - or individual delay adjustments on each C+C FanOut => more complex FanOuts ??

XFEL C+C HARDWARE : MORE INFORMATION / QUESTIONS -2- 9) Connection between C+C Master and FanOuts : - on custom backplane all signals / FEE feedbacks only ?? - use single or double FanOut layer ?? 10) C+C FanOut cards : - separate power on backplane => not TCA-intelligent cards ?? - separate dumb FanOut cards and crate ?? - on / near detector => fewer cables ?? 11) LVDS connectors : - RJ45 – bulky, 4-pairs only, but can use 2x LEDs - Double-stack RJ45 – availability / height ?? - HDMI - size / more signal pairs / more grounds/shielding ?? - Double stack HDMI - size ?? - mini-HDMI ?? 12) Is there any C&C System interface to MPS ( Machine Protection System ) ??