Systems Overview Computer is composed of three main components: CPU Main memory IO devices Refers to page

Memory width and length Memory width: Number of bits stored in each memory register (dictated by width of system bus). Memory length: Number of registers. Refers to page 643 Width Length 2 width = max length

One Bit (One Shot) Storage AND-gate Refers to page

Better One Bit Storage Latch Multiple implementations available (S-R, J-K, D, T, 2NOR) Q can be set, cleared, and remember in-between Refers to page 1185 S R Q Q’ QtSRQt

Types of Memory Memory TypeAccess SpeedRead/Write/Rewrite DRAM50nsYes - Read and Write many times SRAM10nsYes - Read and Write many times ROMWrite Once PROMWrite Once EPROM150nsUV erasable PROM (UV window) EEPROMElectrically erasable PROM (high voltage) FLASHReprogrammable, non-volatile Refers to page 1206

Static Memory (SRAM) Lots of Flip-Flops Fast (<10ns read cycles) Expensive (only used in fast cache) Often “byte-wide” – read one byte at a time Frequency division Refers to page 1217

Frequency Division Refers to page 1218 Three positive-edge triggered T (toggle) Flip-Flops 1 Clock f/2 f/4 11

Dynamic Memory (DRAM) Advantages Single bit storage is a FET and a ~20fF capacitor Equivalent storage of SRAM in ¼ area. Read speeds of 5-50ns Refers to page

Dynamic Memory (DRAM) Disadvantages “Leaky” – loses data unless refreshed (100x a second). Read speeds of 5-50ns….but “rest” period means average read speed of 100ns (10 million reads a second). Recovery period needed for bit lines, a delay known as cycle time. Refers to page

One Bit DRAM Refers to page Word line acts like electrical switch Bit line writes byte Capacitor stores last written bit

One Bit DRAM Write Refers to page Close switch to specify what bit 2. Write “1” 1 3. Open switch to store bit

One Bit DRAM Read Refers to page Close switch to specify what bit 2. Read bit (in this case, 1) 1

DRAM Array Refers to page Word Line 1 Word Line 2 Bit Line 1Bit Line 2

DRAM Array One Bit Read Refers to page Pick this bit to read Close Word Line 2 Switch (Row Address Select) 3. Read Bit Line 2 (Column Address Select)

DRAM Array Row Refresh Refers to page Close Word Line 2 Switch 2. Read all bits to memory...and 3. amplify and rewrite back to appropriate bits.

Dynamic Memory (DRAM) Techniques/Improvements Interleave read operations – read from “even” bank, then “odd” bank, allowing recovery time to take place during read of opposing bank. EDO – Extended Data Output means 4 consecutive column reads for each row address select. SDRAM- Synchronous burst (only send one address, then use on-chip CAS), self-refreshing, selectable burst lengths. Refers to page 12617

DRAM Physical Package (and the kitchen sink) SIMM – Single Inline Memory Module DIMM – Dual Inline Memory Module Small cards with 8-9 DRAM chips (if 9, it’s for parity checking) Available in 256MByte, 512Mbyte, 1GByte (and 2GByte) Each memory cell on each chip contains 8 bits so 8x8=64 bits read every 10ns. Pentium 64 bus can use 16bits each transfer, so each 16bit instruction available every 10/4ns. Voltage used on chips is falling from logic 5V to 2.5V Refers to page 12618