Tutorial 1 Combinational Logic Synthesis

Introduction to VHDL VHDL = Very high speed Hardware Description Language VHDL and Verilog are the industry standards for describing digital systems

Introduction to VHDL Like C++, a working knowledge of VHDL can be gained relatively quickly Like C++, a solid understanding of what you’re writing and why you’re writing it can take years It’s especially important in VHDL to focus not on style and syntax, but on comprehension

Introduction to VHDL VHDL is a HARDWARE DESCRIPTIVE LANGUAGE Every line of code translates directly to hardware

Entities and Architectures Creating a module in VHDL involves creating an entity and an architecture

Entities and Architectures Entity MyEntity is port ( a, b : in std_logic; c : out std_logic); End entity; When you define an entity, you define the black- box structure that’s visible to outside modules a and b aren’t “parameters”. They’re WIRES. c isn’t a ‘return value’. It’s a WIRE.

Entities and Architectures architecture main of MyEntity is begin end archicture; Each entity is actually implemented inside an architecture You can have more than one architecture for each entity, but in general, you should just have one

Component instantiation Other blocks can then use these sub-modules, but first you have to declare it as a component component DFF port(d : in std_logic; q : out std_logic); end component; This component can now be instantiated inside this top-level entity as many times as you want

Component Instantiation A component is instantiated as follows MyDff : DFF Port map (d => foo, q => bar); Foo and bar are signals or ports in the top-level entity d and q are ports of the component being instantiated d is connected to foo with a wire. Likewise with q and bar. MyDFF is a label given to the component instance. VHDL requires all component instances to have unique labels to differentiate between multiple instances of the same component

Combinational Logic A <= B; Textbooks call this a “Concurrent Assignment” This is a WIRE

Combinational Logic A <= B AND C; This is an AND gate, where ‘A’ is the output node and ‘B’ and ‘C’ are input nodes

Combinational Logic A <= B AND C; D <= A; E <= D AND A; What does this look like? Remember, think of this as not code, but a description of a circuit Bonus point: Simplify this logic. What VHDL code would represent your simplified circuit?

Combinational Logic

Select Statements With std_logic_vector’(A,B) select Q<= “0” when “00” <= “0” when “01” <= “1” when “10” <= “0” when “11” <= “0” when others; This LOOKS like a case statement. It can be more accurately described as a “description of a truth table” What does the truth table look like? What does the hardware look like?

Select Statement ABQ

Conditional Assignment Q <= ‘1’ when A = ‘1’ else ‘0’ when B = ‘1’ else ‘0’; This differs from select statements because Conditional Assignment has a priority of conditions. The first condition is evaluated before the second. If A = ‘1’ and B = ‘1’, Q becomes ‘1’, because that condition comes first

Conditional Assignment In evaluating this block, statement priority is considered in populating the truth table The truth table is then used to generate hardware. The hardware itself has no sequential nature. What does the truth table look like? What does the hardware look like? Any conditional assignment can be expressed with a select block

Conditional Assignment ABQ

Combinational Processes Combinational processes do not involve registers. Registered processes are covered in Tutorial 2. Combinational processes allow combinational logic to be described in a sequential way. Any combinational process can be described using concurrent statements (though the code may look uglier)

Combinational Processes process(a) begin b <= a; end process; The bracketed ‘a’ is part of a process’ sensitivity list. This should list out all the signals used as inputs to this process

If-then-else If A = ‘1’ then Q <= ‘0’ Else Q <= ‘1’ End if; This is an if-then-else construct similar to most programming languages It implies a sequential priority, which is similar to conditional assignment

Case Case Sel is when ‘1’ => Q <= ‘1’; when others => Q <= ‘0’; End case The case statement implies no priority, and is similar to the select statement

Combinational Processes So why bother with if-then-else and case statements when you can use selects and conditional assignments? Sometimes what you’re trying to describe is just ‘nicer looking’ or shorter in one or the other