Ob-Chip Networks and Testing1 On-Chip Networks and Testing-II

Ob-Chip Networks and Testing2 Aethereal NoC as Communication Fabric for SoC 1.Goosens et al., “Aetherial Network on Chip...,” IEEE D&T Magazine, Sept-Oct 2005, Vermeulen et al., “Bringing Communication Networks on a Chip: Test and Verification Implications,” IEEE Communications Magazine, Sept. 2003,

Ob-Chip Networks and Testing3 Rationale for Aethereal As SoC complexity grows, its communication infrastructure is a major concern. Expert opinion says NoCs are increasingly likely to be the choice for on-chip communication because they provide structure, modularity, and performance advantages over alternative designs Aethereal NoC is a research product from Philips to explore NoC-based SoC designs. Vermeulen et al. [2] consider an Aethereal-based SoC design for multimedia applications and discuss how it can be tested and verified.

Ob-Chip Networks and Testing4 Example SoC with Aethereal NoC The picture shows routers, network interfaces, processor, memory, and memory- interface cores, and neighbor-links.

Ob-Chip Networks and Testing5 Combined Guaranteed- Throughput (GT) and Best-Effort (BE) Router Conceptual View Hardware View

Ob-Chip Networks and Testing6 Aethereal Chip: Contention-Free Routing Contention-free routing: network of three routers (R1, R2, and R3) at slot s  2, with corresponding slot tables (T1, T2, and T3).

Ob-Chip Networks and Testing7 Default Core-Based Testing The default method assumes the cores are wrapped, according to IEEE1500 and uses dedicated TAMs to transport test data. The example shows cores tested simultaneously by 4 TAMs. Disadvantage: Wire congestion due to TAMs.

Ob-Chip Networks and Testing8 NoC Reuse Based Testing NoC blocks (routers and network interfaces) are tested first (top). If ok then NoC can be used to help test other cores (bottom). Further, because routers are identical, their test data sets can be broadcast and applied concurrently and their responses can be compared to each other for mismatches (for go/no-go testing)

Ob-Chip Networks and Testing9 Reuse-Based Test Scheduling 1.C. Aktouf, “A Complete Strategy for Testing an On-Chip Multiprocessor Architecture,” IEEE D&T, Jan-Feb 2002, C. Liu et al., “Reuse-Based Test Access and Integrated Test Scheduling for NoC,” DATE’06,

Ob-Chip Networks and Testing10 Complete Strategy Summary [1] Homogeneous fine-grain, massively parallel, message-passing, multiprocessor in 2D topology Testing in three phases: 1. Router Testing (by groups of cells) 2. RAM Block Testing (using BIST) 3. Distributed Processor Testing (using PMC model)

Ob-Chip Networks and Testing11 Multiprocessor Architecture Interconnection network on top – shading shows two cells communicating using shared buffers. Cell Structure at the bottom. Each cell consists of Processor, Memory, and Router Messages include relative x and y displacements, address, and data.

Ob-Chip Networks and Testing12 Boundary-Scan Based Testing of Routers in Groups of Cells (GCs) Basic-cell groups (top) and test-circuit configuration for external test (right)

Ob-Chip Networks and Testing13 Reuse-Based Test Access and Test Scheduling [2] Summary 2D mesh architecture similar to [1]. Each cell consists of a core and router. Progressive reuse of network resources for transporting test data Routers and cores tested concurrently

Ob-Chip Networks and Testing14 System Architecture The top picture shows a 12- node system in which a particular SoC (ITC02 benchmark d695) has been mapped to 10 available nodes. Two shaded cores are being tested using dedicated paths from external inputs to the core an from the core to an external output The paper compares results to those in [1] that uses the GC approach (bottom) to testing routers first. 1x1 groups 2x2 groups

Ob-Chip Networks and Testing15 Progressive Scheduling for Router Testing Constraint: Only pretested routers can be reused for test-data transport, hence need for scheduling Test responses are assumed to be processed on-chip or compressed and transported off-chip through dedicated paths The picture shows 2x2 I/O, numbers represent groups of cells that can be tested simultaneously, in increasing order of group numbers. Even though only 10 cells are occupied, for testing all 12 must be tested. Only the router-under-test is in test mode, others on the path are in normal mode. Multicast networkUnicast network

Ob-Chip Networks and Testing16 On-Chip Test Response Processing Using MISRsUsing Comparators

Ob-Chip Networks and Testing17 Integrated Test Scheduling Consider the unicast network scheduling example from before: Assume both bottom row routers have been tested in steps 1, 2, and 3. We can reuse Input 2 and Output 2 to test bottom-row cores; at the same time we can reuse Input1 and Output 1 to test routers in group 4. The paper gives an algorithm for scheduling such integrated testing

Ob-Chip Networks and Testing18 A Sample of Results Col 2: Boundary-scan results from [1] assuming all routers are tested simultaneously - only router testing times are shown Col 3: router testing time when network is reused (Savings over Col 2) Col 4: Test bus results from TAM co-optimization by Iyengar et al. (DATE 2002) – discussed earlier. Col 5: Routers and cores test separately Col 6: Integrated testing (savings over Col 5)

Ob-Chip Networks and Testing19 Conclusion Testing research on NoC-based SoC is still in infancy. Approaches are highly dependent on assumptions about the system and NoC architectures, hence hard to compare against each other. ITRS projections, however, show that NoC is likely to be the dominant communication mechanism of the future SoC, hence this is good field of research to get into.

Ob-Chip Networks and Testing20 Bibliography Goosens et al., “Aetherial Network on Chip...,” IEEE D&T Magazine, Sept-Oct 2005, Vermeulen et al., “Bringing Communication Networks on a Chip: Test and Verification Implications,” IEEE Communications Magazine, Sept. 2003, C. Liu et al., “Reuse-Based Test Access and Integrated Test Scheduling for NoC,” DATE’06, C. Aktouf, “A Complete Strategy for Testing an On-Chip Multiprocessor Architecture,” IEEE D&T, Jan-Feb 2002, Nahvi and Ivanov, “A Packet Switching Communication-Based TAM for SoC,” ETW01,