Prepared by Eng. Musa Alyaman1 Chapter Seven Chapter Seven PIC16F87x

Prepared by Eng. Musa Alyaman2 PIC16F87XA

Prepared by Eng. Musa Alyaman3 Devices Included in this Data Sheet PIC16F873A PIC16F874A PIC16F876A PIC16F877A

Prepared by Eng. Musa Alyaman4 High Performance RISC CPU Only 35 single word instructions to learn All single cycle instructions except for program branches, which are two-cycle Operating speed: DC - 20 MHz clock input DC ns instruction cycle Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM), Up to 256 x 8 bytes of EEPROM Data Memory Pin out compatible to other 28-pin or 40/44-pin PIC16CXXX and PIC16FXXX microcontrollers

Prepared by Eng. Musa Alyaman5 Peripheral Features Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counter with crystal/clock Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler Two Capture, Compare, PWM modules - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection Brown-out detection circuitry for Brown-out Reset (BOR)

Prepared by Eng. Musa Alyaman6 Analog Features 10-bit, up to 8 channel Analog-to-Digital Converter (A/D) Brown-out Reset (BOR) Analog Comparator module with: - Two analog comparators - Programmable on-chip voltage reference (VREF) module - Comparator outputs are externally accessible

Prepared by Eng. Musa Alyaman7 Special Microcontroller Features 100,000 erase/write cycle Enhanced FLASH program memory typical 1,000,000 erase/write cycle Data EEPROM memory typical Data EEPROM Retention > 40 years In-Circuit Serial Programming™ (ICSP™) via two pins Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Programmable code protection Power saving SLEEP mode Selectable oscillator options In-Circuit Debug (ICD) via two pins

Prepared by Eng. Musa Alyaman8 CMOS Technology Low power, high speed FLASH/EEPROM technology Wide operating voltage range (2.0V to 5.5V) Commercial and Industrial temperature ranges Low power consumption

Prepared by Eng. Musa Alyaman9 PIC16F87XA DEVICE FEATURES

Prepared by Eng. Musa Alyaman10 The Core 16F873/16F876

Prepared by Eng. Musa Alyaman11 The Core 16F874/16F877

Prepared by Eng. Musa Alyaman12 Program Memory

Prepared by Eng. Musa Alyaman13 Program Memory Paging PCL and PCLATH The program counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC ) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. The following Figure shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH → PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH → PCH).

Prepared by Eng. Musa Alyaman14 Program Memory Paging

Prepared by Eng. Musa Alyaman15 Program Memory Paging COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). STACK The PIC16F87XA family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Call & Goto All PIC16F87XA devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH bits is not required for the return instructions (which POPs the address from the stack).

Prepared by Eng. Musa Alyaman16 Program Memory Paging

Prepared by Eng. Musa Alyaman17 Program Memory Paging

Prepared by Eng. Musa Alyaman18 Program Memory Paging

Prepared by Eng. Musa Alyaman19 Data Memory

Prepared by Eng. Musa Alyaman20 DIRECT/INDIRECT ADDRESSING

Prepared by Eng. Musa Alyaman21 CONFIGURATION WORD (ADDRESS 2007h)

Prepared by Eng. Musa Alyaman22 Status Register

Prepared by Eng. Musa Alyaman23 INTERRUPT LOGIC

Prepared by Eng. Musa Alyaman24 INTCON Register

Prepared by Eng. Musa Alyaman25 PIE1 Register

Prepared by Eng. Musa Alyaman26 PIR1 Register

Prepared by Eng. Musa Alyaman27 PIE2 Register

Prepared by Eng. Musa Alyaman28 PIR2 Register

Prepared by Eng. Musa Alyaman29 References 1. An Introduction to the Design of Small-Scale Embedded Systems, 1st Ed. By: Tim Wilmshurst Palgrave, The PIC Microcontroller Book 3. Computer Organization & Design by Patterson & Hennessy. 4. Intel Website MicroChip web site 6. The PIClist internet site.