1. PIC 16F877

2. Outline Introduction Why PIC? Why Not PIC? 16F877Architecture
Instruction Set
Software Development Tools
Hardware Development Tools
Simple Programs
Peripherals
Using Peripherals ..
Practice Session

3. Introduction What is a microcontroller ? – CPU – Peripherals
– Boolean logic
– Many more features…
on a single chip is a microcontroller.

4. Why microcontroller ?
– Small Size (single chip solution)
– Low Cost
– Bit Manipulation (Code reduction)
– Timing Problems Vanish
– Reliability of product increases
– A lot of variety available (8 pin to 100+)
– Code Security

5. Applications
– PC keyboard
– Mouse
– Mobile
– UPS
– TV, fridge, oven washing machine
– Automobiles
– Industrial automation
– Almost every miniature intelligent device

6. What is PIC? PIC = Peripheral Interface Controller
Produced by Microchip, USA
PIC is simply a microcontroller useful for
industrial intelligent system design.

7. PIC has a lot of variety
– 8 pin to 100+ pins
– 512 Bytes to 32+ KB of ROM
Many versions have EEPROM
Features suitable for industrial design
– WDT and Brownout reset
More current source/sink for port pins
Many chip configuration options
Analog Peripherals
Easy to learn, Easily available

8. One needs to spend at least some time to
do serious product development
No external memory support
– For small and medium range
Produced by ‘only’ Microchip

9. Conclusion It depends on – The designer, – The tools he has
– His expertise
– Requirements of the product …
– Cost of the product
It is better to use the suitable microcontroller for the product and start product designing (Instead of debating which is better …)

10. 16F877 16 is the series – Others are 12,14,17,18
‘F’ stands for ‘Flash’ program memory
– ‘C’ is used for OTP versions
877 is the product code

11. CPU Features High-performance RISC CPU
Only 35 single word instructions to learn
– RISC controller
All single cycle instructions except for program
branches which are two cycle
Operating speed: DC - 20 MHz clock input
Up to 8K x 14 words of FLASH Program Memory
Up to 368 x 8 bytes of Data Memory (RAM)

12. CPU Features Up to 256 x 8 bytes of EEPROM data memory
Pin-out compatible to the 16C73B/74B/76/77
Interrupt capability (up to 14 sources)
Eight level deep hardware stack
Direct, indirect and relative addressing modes

13. CPU Features Power-on Reset (POR) Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
Programmable code-protection

14. CPU Features Power saving SLEEP mode Selectable oscillator options
Low-power, high-speed CMOS FLASH/
EEPROM technology
Fully static design

15. CPU Features In-Circuit Serial Programming (ICSP) via two pins
Single 5V In-Circuit Serial Programming capability
In-Circuit Debugging via two pins
Processor read/write access to program memory
Wide operating voltage range: 2.0V to 5.5V

16. CPU Features High Sink/Source Current: 25 mA
Commercial and Industrial temperature ranges
Low-power consumption:
– < 2 mA 5V, 4 MHz
– 20 uA 3V, 32 kHz
– < 1 uA typical standby current

17. Peripheral Features Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler,
– can be incremented during sleep via external crystal/clock
Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

18. Peripheral Features Two (Capture, Compare, PWM) modules
– Capture is 16-bit, max. resolution is 12.5 ns
– Compare is 16-bit, max. resolution is 200 ns
– PWM max. resolution is 10-bit

19. Peripheral Features 10-bit multi-channel Analog-to-Digital converter
Synchronous Serial Port (SSP) with SPI (Master Mode) and I2C (Master/Slave)
Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection

20. Peripheral Features
Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44- pin only)
Brown-out detection circuitry for Brown-out Reset (BOR)

23. Program Memory • Harvard Architecture
– Separate Code and Data memory space
13 bit PC
– 8 KB Program memory with 4 banks of 2K each
Word Size is 14 bit
8 Level deep hardware stack
– Security
– No Push-Pop Instructions
– Assembler/compiler gives warning if limit is crossed

24. Reset Vector = 0000H
Interrupt Vector = 0004H
– Single Vector for all sources
(+) Priority can be changed
( - ) Different Interrupt latency for different sources.

25. Data Memory 368 Bytes Divided into 4 banks
– Bank selection needs to be done before accessing memory location
Upper area of each bank is occupied by SFRs
Lower area is user’s data area.
The data area is also referred as “Register File Area”

27. Bank selection is done using 2 bits in the SFR called as STATUS register
Status <6:5> are referred as RP1 and RP0
RP1:RP0 => 00 => Bank 0
RP1:RP0 => 01 => Bank 1
RP1:RP0 => 10 => Bank 2
RP1:RP0 => 11 => Bank 3
Status register is available in all 4 banks

29. PORTA and TRISA PORTA is the port register
TRISA is the direction register for PORTA
– Each pin of PORTA can be individually made input or output
– The port A pin will be input if the corresponding bit in TRISA is HIGH.
– TRISA = 0FFH => PORTA all pins input
– TRISA = 00H => PORTA all pins output
– TRISA = 0FH => upper nibble output lower nibble
input

30. Similarly all the other port pins can be set as output or input under the control of user program.
By default all ports are input.

31. Program Counter PCL is readable as well as writeable
Write to Program Counter
PCL is readable as well as writeable
PCH is not readable, it is indirectly writable through PCLATH

32. Concept of Paging
Branching instructions can jump in anywhere in 2k bytes of memory area
2k => 11 bit address is present in instruction

33. Direct Addressing

34. Indirect Addressing
Two Registers
FSR
INDF

35. Instruction Set

36. Instruction Set Only 35 Instructions – Byte Oriented – Bit Oriented
– Literal and Control
Notations used
– f : File specified
– k : Immediate data
– w: Working Register
– d : Destination 0: w, 1:file
– b: Bit position in register

37. Data Movement Move Immediate value into w register – MOVLW 45H
– MOVLW 0x45
– MOVLW b’ ’
– MOVLW STATUS
Move W to File (Register)
– MOVWF <Address>
– MOVWF PORTA
– MOVWF TRISA

38. Bit Set Reset All the data memory is bit oriented.
– Any bit of any data memory can be individually set or reset.
BCF f, b and BSF f, b
BCF PORTB, 5
BSF PORTB, 7
BCF STATUS, 5
BSF STATUS, 6
– Used for bank selection

39. Other Instructions Instructions for Data Movement

40. CLRF Clear the specified file – Syntax: [ label] CLRF f
– Operands: 0 < f < 127
– Operation: 00h => (f)
– Z => 1
– Status Affected: Z
– Description:
The contents of register ‘f’ are cleared and the Z bit is set.
– Example:
CLRF PORTB
CLRF 70H

41. CLRW Clear W register – Syntax: [ label ] CLRW – Operands: None
– Operation: 00h => (W)
– Z => 1
– Status Affected: Z
– Description:
W register is cleared. Zero bit (Z) is set.

42. CLRWDT Clear Watchdog Timer – Syntax: [ label ] CLRWDT
– Operands: None
– Operation: 00h => WDT ; 0 => WDT prescaler
– 1 => TO; 1 => PD
– Status Affected: TO, PD
– Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.

43. MOVF Move specified file to specified dest.
– Syntax: [label ] MOVF f, d
– Operands: 0 < f < 127 d is [0,1]
– Operation: (f) => (destination)
– Status Affected: Z
– Description: The contents of register f are moved to a destination dependent upon the status of d. If d = , destination is W register. If d = 1, the destination is file register f itself. D = 1 is useful to test a file register since status flag Z is affected.
– Example:
MOVF PORTB, W
MOVF 70H, F

44. SWAPF Swap nibbles in specified file – Syntax: [ label ] SWAPF f, d
– Operands: 0 < f < 127 d is [0,1]
– Operation: (f<3:0>) => (destination<7:4>), and
(f<7:4>) => (destination<3:0>)
– Status Affected: None
– Description:
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W register. If 'd' is 1, the result is placed in register 'f'.
– Example:
SWAP 70H, F

45. COMF COMF: Complement f – Syntax: [ label ] COMF f, d
– Operands: 0 < f < 127 d is [0,1]
– Operation: (/f) => (destination)
– Status Affected: Z
– Description:
The contents of register ‘f’ are complemented. If ‘d’ is 0, the result is stored in W. If ‘d’ is 1, the result is stored back in register ’f’.
– Example:
COMF PORTB

46. Test Write an instruction to Clear location 0x77 Clear Watchdog Timer
Move data at 0x54 into W
Exchange nibbles of PORTB
Invert all the bits of location
0x78
Load 00 into W register
CLRF 0x77
CLRWDT
MOVF 0x54, W
SWAPF PORTB
COMF 0x78
CLRW

47. Instructions for Addition / Subtraction

48. ADDLW ADDLW: Add Literal and W – Syntax: [ label] ADDLW k
– Operands: 0 < k < 255
– Operation: (W) + k => (W)
– Status Affected: C, DC, Z
– Description:
The contents of the W register are added to the eight bit literal ‘k’ and the result is placed in the W register.

49. ADDWF ADDWF: Add W and f – Syntax: [ label] ADDWF f , d
– Operands: 0 < f < 127 d = [0 or 1]
– Operation: (W) + (f) => (destination)
– Status Affected: C, DC, Z
– Description: Add the contents of the W register with register ‘f’. If ‘d’ is 0, the result is stored in the W register. If ‘d’ is 1, the result is stored back in register ‘f’.

50. SUBLW SUBLW: Subtract W from Literal – Syntax: [ label ] SUBLW k
– Operands: 0 < k < 255
– Operation: k - (W) => (W)
– Status Affected: C, DC, Z
– Description:
The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.

51. SUBWF Subtract W from f – Syntax: [ label ] SUBWF f, d
– Operands: 0 < f < 127 d is [0,1]
– Operation: (f) - (W) => (destination)
– Status Affected: C, DC, Z
– Description: Subtract (2’s complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
– Example:
SUBWF 70H, F

52. Test Write instructions to Load (0x70) with 0x55 MOVLW 0x55 MOVWF 0x70
Add (PORTA) and (0x71)
Subtract W from 0x65
Put result on PORTB
MOVLW 0x55
MOVWF 0x70
MOVF PORTA,W
ADDWF 0X71,W
SUBLW 0x65
MOVWF PORTB

53. Instructions for Logical Operations

54. ANDLW ANDLW: AND Literal with W Syntax: [ label] ANDLW k
Operands: 0 < k < 255
Operation: (W) AND k => (W)
Status Affected: Z
Description:
The contents of W register are ANDed with the eight bit literal 'k'. The result is placed in the W register.

55. ANDWF ANDWF: AND W with f Syntax: [ label] ANDWF f, d
Operands: 0 < f < 127 d is [0 or 1]
Operation: (W) AND (f) => (destination)
Status Affected: Z
Description:
AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.

56. IORLW Inclusive OR Literal with W Syntax: [ label ] IORLW k
Operands: 0 < k < 255
Operation: (W) OR k => (W)
Status Affected: Z
Description: The contents of the W register are ORed with the eight bit literal 'k'. The result is placed in the W register.
Example:
IORLW 0xF0

57. IORWF Inclusive OR W with f Syntax: [ label ] IORWF f, d
Operands: 0 < f < 127 d is [0,1]
Operation: (W) OR (f) => (destination)
Status Affected: Z
Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
Example:
IORWF PORTB, F
IORWF 0x70, W

58. XORLW Exclusive OR Literal with W Syntax: [ label] XORLW k
Operands: 0 < k < 255
Operation: (W) XOR k => (W)
Status Affected: Z
Description: The contents of the W register are XORed with the eight bit literal 'k'. The result is placed in the W register.
Example:
XORLW 0x0F

59. XORWF Exclusive OR W with f Syntax: [ label] XORWF f, d
Operands: 0 < f < 127 d is [0,1]
Operation: (W) XOR (f) => (destination)
Status Affected: Z
Description: Exclusive OR the contents of W register with register 'f'. If ‘d’ 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
Example:
XORWF PORTB, W

60. Instructions for Bit Manipulation / Bit testing

61. BCF BCF: Bit Clear f Syntax: [ label] BCF f, b
Operands: 0 < f < 127
b = any value between 0 to 7 (inclusive of both)
Operation: 0 => (f <b>)
Status Affected: None
Description: Bit 'b' in register 'f' is cleared.
Example:
BCF PORTB, 4

62. BSF BSF: Bit Set f Syntax: [ label] BSF f, b
Operands: 0 < f <127
b = any value between 0 to 7 (inclusive of both)
Operation: 1 => (f <b>)
Status Affected: None
Description: Bit 'b' in register 'f' is set.
Example:
BSF PORTB, 4

63. BTFSS
Test the specified bit in specified file. Skip the next instruction if the bit is Set
Syntax: [ label] BTFSS f, b
Operands: 0 < f < , 0 < b < 7
Operation: skip if (f <b>) = 1
Status Affected: None
Description: If bit ’b’ in register ’f’ is ’0’, the next instruction is executed. If bit ’b’ is ’1’, then the next instruction is discarded and a NOP is executed instead making this a 2TCY instruction.
Example:
BTFSS PORTC, 3

64. BTFSC
Test the specified bit in specified file. Skip the next instruction if the bit is Clear
Syntax: [ label] BTFSC f, b
Operands: 0 < f < < b < 7
Operation: skip if (f <b>) = 0
Status Affected: None
Description: If bit ’b’ in register ’f’ is ’1’, the next instruction is executed. If bit ’b’, in register ’f’, is ’0’, the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction.
Example:
BTFSC PORTB, 5

65. Instructions for Call / Return

66. GOTO Unconditional Branch Syntax: [ label ] GOTO k
Operands: 0 < k < 2047
Operation: k => PC<10:0>
PCLATH<4:3> => PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction.
Example:
GOTO LABEL

67. CALL Call Subroutine Syntax: [ label ] CALL k
Operands: 0 < k < 2047
Operation: (PC)+ 1 => Top of Stack, k => PC<10:0>, (PCLATH<4:3>) => PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction.

68. RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None
Operation: TOS => PC
Status Affected: None
Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction

69. RETLW Return with Literal in W Syntax: [ label ] RETLW k
Operands: 0 < k < 255
Operation: k => (W) Top of Stack (ToS) => PC
Status Affected: None
Description: The W register is loaded with the eight bit literal ’k’. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction.

70. RETFIE Return from Interrupt Syntax: [ label ] RETFIE Operands: None
Operation: Top of Stack (ToS) => PC,
1 => GIE (IMP)
Status Affected: None

71. Instructions for Loops

72. DECF Decrement file Syntax: [ label] DECF f, d
Operands: 0 < f < 127 d is [0,1]
Operation: (f) - 1 => (destination)
Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is 0, the result is stored in the W register. If ‘d’ is 1, the result is stored back in register ‘f’.

73. INCF Increment file Syntax: [ label ] INCF f, d
Operands: 0 < f < 127 d is [0,1]
Operation: (f) + 1 => (destination)
Status Affected: Z
Description: The contents of register ‘f’ are incremented. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is 1, the result is placed back in register ‘f’.

74. DECFSZ Decrement file, Skip the next instruction if file contains 0
Syntax: [ label ] DECFSZ f, d
Operands: 0 < f < 127 d is [0,1]
Operation: (f) - 1 => (destination); skip if result = 0
Status Affected: None
Description: The contents of register ’f’ are decremented. If ’d’ is 0, the result is placed in the W register. If ’d’ is 1, the result is placed back in register ’f’. If the result is 1, the next instruction is executed. If the result is 0, then a NOP is executed instead making it a 2TCY instruction.

75. INCFSZ Increment file, Skip the next instruction if file contains 0
Syntax: [ label ] INCFSZ f, d
Operands: 0 < f < 127 d is [0,1]
Operation: (f) + 1 => (destination), skip if result = 0
Status Affected: None
Description: The contents of register ’f’ are incremented. If ’d’ is 0, the result is placed in the W register. If ’d’ is 1, the result is placed back in register ’f’. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead making it a 2TCY instruction.

76. Instructions for Rotate

77. RLF Rotate Left file through Carry Syntax: [ label ] RLF f, d
Operands: 0 < f < 127 d is [0,1]
Status Affected: C
Description: The contents of register ‘f’ are rotated one bit to the left through the Carry Flag. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is 1, the result is stored back in register ‘f’.

78. RRF Rotate Right file through Carry Syntax: [ label ] RRF f, d
Operands: 0 < f < 127 d is [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is 1, the result is placed back in register ‘f’.

79. Note.. There is no shift right/left instruction
Use rotate with carry kept cleared.

80. Miscellaneous Instructions

81. NOP
No Operation
To kill time
Useful for small delays

82. SLEEP The chip goes in standby mode Syntax: [ label ] SLEEP
Operands: None
Operation: 00h => WDT, 0 => WDT prescaler,
1 => TO, 0 => PD
Status Affected: TO, PD
Description: The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped.