Gerousis Toward Nano-Networks and Architectures C. Gerousis and D. Ball Department of Physics, Computer Science and Engineering Christopher Newport University Newport News, VA 23606

Gerousis2 1015/MAPLD 2005 Nanoelectronic Architectures Limits of Conventional CMOS technology - Device physics scaling, power dissipation - Interconnects Nanoelectronic Integrated Circuits Present Work -Simulation of nano networks synthesized from single-electron tunneling transistors (SETs) -Demonstration of SET-CNN and SET neural applications - Hybrid circuits of ultrascale CMOS coupled to locally connected cellular nonlinear networks (CNNs) of nanodevices for special purpose processing

Gerousis3 1015/MAPLD 2005 Nanoelectronic Integrated Circuit CMOS drivers for fan-out Single-electron transistors as processing elements Photo-detector CMOS and SETs are rather complementary: SET is the winner of low-power consumption and of new functionality while the advantages of CMOS such as high-speed, driving, voltage gain and input impedance can makeup for exactly for the SET's intrinsic shortcomings.

Gerousis4 1015/MAPLD 2005 Single-Electron Transistor A single-electron tunneling (SET) transistor composed of a conducting island (or quantum dot) between two tunnel junctions characterized by junction capacitances, C s and C d, and tunneling resistances, R s and R d.

Gerousis5 1015/MAPLD 2005 Electron tunneling is suppressed due to the Coulomb charging energy, e 2 /2C. A separate gate voltage changes the charge state of the dot (island), and periodically lifts the Coulomb blockade allowing tunneling. EFlEFl EFrEFr ee G/G max V g (e/C g ) Single-Electron Transistor Si SOI Single Electron Transistor: D. H. Kim et al., IEEE Trans. ED 49, 2002

Gerousis6 1015/MAPLD 2005 Monte Carlo simulation of SET circuits The Master Equation for a set of N dots (islands) in terms of the multi-island distribution function is given by where the tunneling rate depends on change of total free energy of systems after tunneling

Gerousis7 1015/MAPLD 2005 Average quantities such as current in a two junction system are given as averages Single electron tunnel events modeled as instantaneous events which are generated stochastically using the calculated tunneling rates for all possible events across all junctions, and using the computer random number generator where r is random number 0,1 and t r is the random time between tunneling events. After tunneling, the new tunnel rates are computed, and the next tunneling event generated. The time evolution according to the master equation is modeled as random walk. Monte Carlo simulation of SET circuits

Gerousis8 1015/MAPLD 2005 ‘SIMON’ (SIMulation Of Nano structures) C. Wassshuber and H. Kosina, "SIMON: A Single-Electron Device and Circuit Simulator", Superlattices and Microstructures 21, 37 (1997).

Gerousis9 1015/MAPLD 2005 SET Cellular Nonlinear Networks Feedforward synapses Feedback synapses x ij A non-linear architecture suitable for SET devices is a locally interconnected CNN type array structure for use in array processing such as image processing applications. The center cell, C ij, receives a weighted feedforward signal b kl u kl and a weighted feedback signal a kl y kl from each neighboring cell C kl.

Gerousis /MAPLD 2005 Cell state equation: x y 1 Cell output equation: Transfer function: Cellular Nonlinear Networks

Gerousis /MAPLD 2005 C 12 =C 23 =0.55aF C 11 =C 22 = C 22 =0.1aF Template: Single-Electron Cellular Network - Shadowing

Gerousis /MAPLD 2005 Threshold Gate in SET Networks Model of a TLG with SET technology (Lageweg et al.)  A threshold gate can be described by the following equations: where ω are the weights, x represents the inputs, and ψ is the threshold

Gerousis /MAPLD 2005 Threshold Gate - SET inverter Model of a TLG with SET technology (Lageweg et al.)

Gerousis /MAPLD 2005 Network for Recognition of Bit Pattern V1V1 V2V2 V3V3 V4V4 V out

Gerousis /MAPLD 2005 Network for Recognition of Bit Pattern V1V1 V2V2 V3V3 V4V4 V out

Gerousis /MAPLD 2005 Number Recognition Sub-Networks

Gerousis /MAPLD 2005 Number Recognition Test Circuit The network contains several levels/layers of hidden operations between input and output. These layers include row detection, number recognition, and encoding.

Gerousis /MAPLD 2005 MS1S ≥311 M2 M1 M2 M3 M4 Number Recognition Test Circuit Input Matrices for V0-V19:

Gerousis /MAPLD Number Recognition Network – Results

Gerousis /MAPLD 2005 A neural nanoelectronics architecture with a low interconnection density, such as cellular neural networks (CNNs) are implemented in analog circuit techniques so that low power applications, such as intelligent sensor pre- processing are preferred applications. Limitations: - Small capacitance values required for room- temperature operation. - SET weights are hard wired by the use of capacitive connections, which limits the range of applications. - The charge sensitivity of the devices also imposes strong limitations on the allowable electrostatic interaction between different devices in a ULSI circuit. Conclusions