1. UPoN Lyon 2008 G. Albareda 1 G.Albareda, D.Jimenez and X.Oriols Universitat Autònoma de Barcelona - Spain E.mail: Guillem.albareda@uab.cat Can analog and digital applications tolerate the intrinsic noise for aggressively scaled field-effect transistors? Lyon, FRANCE June 2-6, 2008

2. UPoN Lyon 2008 G. Albareda 2 I.1.- Intrinsic noise in ballistic nanoscaleFETs I.2.- Analytical Signal-to-noise ratio (S/N) II.- Monte Carlo simulation of 3D, 2D and 1D FETs III.- Conclusions I.3.- Analytical Bit-error ratio (BER) I.- Introduction: 3D, 2D and 1D ballistic nanoscale FETs Outline II.1.- Simulator description II.2.- Numerical results

3. UPoN Lyon 2008 G. Albareda 3 I.1.- Intrinsic noise in ballistic 3D, 2D and 1D FETs The size of the transistors shrinks for faster and smaller microchips Ly Lz Lx 1,2,3,4 gates to improve gate control (Lx>Ly,Lz) When Ly and Lz become comparable to the electron de Broglie wavelength, the wave- nature of the electron is manifested. Ly Lz 3D Bulk FET Ly Lz 2D Quantum Well FET Ly Lz 1D Quantum-Wire FET 1,2,3,4 gates to improve gate control (Lx>Ly,Lz)

4. UPoN Lyon 2008 G. Albareda 4 I.1.- Intrinsic noise in ballistic 3D, 2D and 1D FETs Study the noise performance of these aggressively scaled FET in analog and digital circuit applications We only consider the “intrinsic” sources of noise due to electron-electron interactions (intrinsic field-effect) We consider ballistic (“ideal”) FETs: No phonon scattering No surface roughness No impurity scattering OUR GOAL.- The Coulomb interaction in the active region I(t).- Exclusion (Pauli) interaction in the contacts

5. UPoN Lyon 2008 G. Albareda 5 I.2.- Signal to noise ratio (S/N) RLRL Analog FET amplifier G  0 3D  30 x 10 x 8 nm 3

6. UPoN Lyon 2008 G. Albareda 6 RLRL RLRL I.2.- Signal to noise ratio (S/N) Analog FET amplifier In the saturation region G  0: Using the superposition principle: For NSNS D S I DS (t)  I DS (t) G  I DS (t)

7. UPoN Lyon 2008 G. Albareda 7 I.2.- Signal to noise ratio (S/N) The role of electron confinement on the average and noise current Ly Lz Lx S D S D S/N 3D > S/N 1D

8. UPoN Lyon 2008 G. Albareda 8 V CC ‘1’ V CC ‘0’ ON OFF ‘1’ noisy noisless P P N NN N Digital FET inverter: ViVi VoVo V th 0 1 Bit error ratio (BER): I.3.- Bit error ratio (BER) in digital applications I DS (t)  0 NSNS D S I DS (t)  I DS (t) G C

9. UPoN Lyon 2008 G. Albareda 9 NSNS D S I DS (t)  I DS (t) G C V CC ‘1’ V CC ‘0’ ON OFF ‘1’ noisy noisless P P N NN N I.3.- Bit error ratio (BER) in digital applications Thermal noise: Voltage fluctuations: Noise Power: ViVi VoVo V th 0 1 Bit error ratio (BER): A/2 [ref] L.B.Kish, Physics Letters A 305 (2002) 144-149.  I DC C 3D > C 1D  BER 3D < BER 1D

10. UPoN Lyon 2008 G. Albareda 10 II.- Monte Carlo simulation of 3D, 2D and 1D FETs III.- Conclusions I.- Introduction: 3D, 2D and 1D nanoscale FETs Outline II.1.- Simulator description: II.2.- Numerical results: II.2.1.- Average current II.2.2.- Signal to noise ratio II.2.3.- Bit error ratio II.1.1.- Confined particles in 1D FETs II.1.2.- Exact 3D Coulomb interaction II.1.3.- Electron injection model with “Pauli” correlations and charge neutrality

11. UPoN Lyon 2008 G. Albareda 11 1-D No electron confinement Ly Lz Lx z y Silicon (100) channel orientation Lx=15 nm Ly=5 nm Lz=2 nm Quantum potential for the x system Guess: This guess is quite accurate when there is only one relevant quantized energy II.1.1.- Confined particles in 1D FETs x y E [ref] X.Oriols, Physical Review Letters, 98, 066803 (2007)

12. UPoN Lyon 2008 G. Albareda 12 II.1.2.- Exact 3D Coulomb interaction 3D Coulomb interaction beyond the mean-field approximation [ref] G.Albareda et al, J. Comp. Electr. (2008) DX ERROR Long- range Long-range +Short-range # e - per cell > 1 # e - per cell = 0 or 1 1nm-5nm mean-field (1 Poisson Eq.) exact-field (N Poisson Eqs.) Long-range Mean-field SEPARABLE Exact term NOT SEPARABLE Long-range + Short-range

13. UPoN Lyon 2008 G. Albareda 13 t I(t) e e e Temperature ; T>0 0 Binomial injection process Pauli correlation [ref] X.Oriols et al. Solid State Electronics, 51, 306 (2007) [ref] T.Gonzalez, Semicond. Sci. Technol. 14, L37 (1999) II.1.3.- Electron Injection model with “Pauli” correlation and charge neutrality Time-dependent version of Landauer-Buttiker boundary conditions

14. UPoN Lyon 2008 G. Albareda 14 Our injection model, coupled to the boundary conditions of the Poisson equation, does also assures charge neutrality at the contacts For a good conductor Local Gauss equation Continuity equation Practical Monte Carlo implementation II.1.3.- Electron Injection model with “Pauli” correlation and charge neutrality  t [ref] H.Lopez, G.Albareda et al., J. Comp. Electr. (2008) =/=/ Charge neutrality At each time step:

15. UPoN Lyon 2008 G. Albareda 15 II.2.1.- Average current Average current No scaling rule: SiO 2 oxide thickness: t ox =2 nm Contact doping: 2·10 19 cm -3 Vdrain Vgate 3D  30 x 10 x 8 nm 3 1D  15 x 5 x 2 nm 3 =0.5V =0.35V ‘0’  0V ‘1’  0.5V

16. UPoN Lyon 2008 G. Albareda 16 II.2.2.- Signal-to-noise ratio Amplifying configuration (saturation region) S/N comparison Vdrain=0.5 V Vgate 3D Average current > 1D Average current 3D Fano Factor < 1D Fano Factor

17. UPoN Lyon 2008 G. Albareda 17 Vgate=0.5 V E fd E Cd E fs E Cs II.2.3.- Bit-error-degradation BER error probability 1 0 1 5ns simulations (time step=2·10 -16 )

18. UPoN Lyon 2008 G. Albareda 18 II.2.3.- Bit-error-degradation BER error probability Vgate=0.5 V 1D 3D 50GHz 500GHz 1THz 500GHz 50GHz 5THz C=5·10 -18 F C=1·10 -18 F Our 3D FETs can hold frequencies up to 500GHz Our 1D FETs can’t hold frequencies of 500GHz According to our analitycal estimation, smaller FETs (capacitors) are noisier.

19. UPoN Lyon 2008 G. Albareda 19 III.- Conclusions Merci beaucoup We have developed an accurate Monte Carlo simulator for 3D, 2D and 1D nanoscale FET. For analog applications, smaller devices produce a minor average current and a larger Fano factor, leading to a signal-to-noise (S/N) degradation. For digital applications, smaller devices are more sensible to electrostatics (i.e. smaller capacitance), and provide a degradation of the Bit Error Ratio (BER). In summary, Smaller FETs are noiser for either analog or digital applications.