April 8/9, 2003 Green Bank GBT PTCS Conceptual Design Review Ron DuPlain, Scott Ransom, Paul Demorest, Patrick Brandt, John Ford, Amy Shelton CASPER information.

Slides:



Advertisements
Similar presentations
Automated Gateware Discovery Using Open Firmware
Advertisements

Progress With iBOBs at Jodrell Bits & Bytes Meeting, JBO, th Dec 2007 Jonathan Hargreaves Electronic Engineer, Jodrell Bank Observatory.
West Coast Spectrometer Team Mark Wagner, Berkeley project manager, FPGA designer Terry Filiba, data transport: FPGA --> CPU --> GPU Suraj Gowda, boosting.
StreamBlade SOE TM Initial StreamBlade TM Stream Offload Engine (SOE) Single Board Computer SOE-4-PCI Rev 1.2.
April 8/9, 2003 Green Bank GBT PTCS Conceptual Design Review John Ford August 5, 2008 CICADA Project The NRAO is operated for the National Science Foundation.
NAIC Visiting Committee Meeting · March 4-6, 2008 FPGA SPECTROMETER COMMISSIONING Spectrometer description How it will be used Where we are at. What needs.
Basic Input Output System
Shilpa Bollineni, Glen Langston, John Ford, Randy McCullough and Paul Demorest DATA ACQUISITION ON THE 43M TELESCOPE.
BEEKeeper Remote Management and Debugging of Large FPGA Clusters Terry Filiba Navtej Sadhal.
Department of Electrical and Computer Engineering Texas A&M University College Station, TX Abstract 4-Level Elevator Controller Lessons Learned.
Software Frameworks for Acquisition and Control European PhD – 2009 Horácio Fernandes.
1.1 Installing Windows Server 2008 Windows Server 2008 Editions Windows Server 2008 Installation Requirements X64 Installation Considerations Preparing.
Detector Array Controller Based on First Light First Light PICNIC Array Mux PICNIC Array Mux Image of ESO Messenger Front Page M.Meyer June 05 NGC High.
Kabuki 2800 “a real-time digital audio effects system for performance” team “Big Country” presents ECEN4610 Preliminary Design Review 14 September 2006.
Using FPGAs with Embedded Processors for Complete Hardware and Software Systems Jonah Weber May 2, 2006.
Atacama Large Millimeter/submillimeter Array Expanded Very Large Array Robert C. Byrd Green Bank Telescope Very Long Baseline Array Digital Signal Processing.
Virtual Network Servers. What is a Server? 1. A software application that provides a specific one or more services to other computers  Example: Apache.
–Streamline / organize Improve readability of code Decrease code volume/line count Simplify mechanisms Improve maintainability & clarity Decrease development.
Atacama Large Millimeter/submillimeter Array Expanded Very Large Array Robert C. Byrd Green Bank Telescope Very Long Baseline Array Spectrometer PDR John.
GallagherP188/MAPLD20041 Accelerating DSP Algorithms Using FPGAs Sean Gallagher DSP Specialist Xilinx Inc.
- 1 - A Powerful Dual-mode IP core for a/b Wireless LANs.
Ross Brennan On the Introduction of Reconfigurable Hardware into Computer Architecture Education Ross Brennan
Highly Scalable Packetised correlators Jason Manley CASPER workshop 2009.
COEN 252 Computer Forensics
DCS Overview MCS/DCS Technical Interchange Meeting August, 2000.
DLS Digital Controller Tony Dobbing Head of Power Supplies Group.
FPGA-based Dedispersion for Fast Transient Search John Dickey 23 Nov 2005 Orange, NSW.
Atacama Large Millimeter/submillimeter Array Expanded Very Large Array Robert C. Byrd Green Bank Telescope Very Long Baseline Array A New Multibeam Spectrometer.
Atacama Large Millimeter/submillimeter Array Expanded Very Large Array Robert C. Byrd Green Bank Telescope Very Long Baseline Array The VLBA Sensitivity.
Nov 1, 2011 RN - 1 Jet Propulsion Laboratory California Institute of Technology Implementation Issues and Choices for VLBI data Acquisition System in DSN.
Atacama Large Millimeter/submillimeter Array Expanded Very Large Array Robert C. Byrd Green Bank Telescope Very Long Baseline Array The VLBA Sensitivity.
Next Generation Digital Back-ends at the GMRT Yashwant Gupta Yashwant Gupta National Centre for Radio Astrophysics Pune India CASPER meeting Cambridge.
Nov 3, 2009 RN - 1 Jet Propulsion Laboratory California Institute of Technology Current Developments for VLBI Data Acquisition Equipment at JPL Robert.
APSR: digital signal processing at Parkes Willem van Straten, Andrew Jameson and Matthew Bailes Centre for Astrophysics & Supercomputing Third ATNF Gravitational.
Part A Presentation Implementation of DSP Algorithm on SoC Student : Einat Tevel Supervisor : Isaschar Walter Accompanying engineer : Emilia Burlak The.
Atacama Large Millimeter/submillimeter Array Expanded Very Large Array Robert C. Byrd Green Bank Telescope Very Long Baseline Array CASPER Workshop 2009.
Australian Astronomy MNRF Development of Monolithic Microwave Integrated Circuits (MMIC) ATCA Broadband Backend (CABB)
Real-time Acquisition and Processing of Data from the GMRT Pulsar Back- ends Ramchandra M. Dabade (VNIT, Nagpur) Guided By, Yashwant Gupta.
An FX software correlator for VLBI Adam Deller Swinburne University Australia Telescope National Facility (ATNF)
Xiangming Sun1PXL Sensor and RDO review – 06/23/2010 STAR XIANGMING SUN LAWRENCE BERKELEY NATIONAL LAB Firmware and Software Architecture for PIXEL L.
Atacama Large Millimeter/submillimeter Array Karl G. Jansky Very Large Array Robert C. Byrd Green Bank Telescope Very Long Baseline Array GBT Control System.
Jason Manley, Aaron Parsons, Don Backer, Henry Chen, Terry Filiba, David MacMahon, Peter McMahon, Arash Parsa, Andrew Siemion, Dan Werthimer, Mel Wright.
The Main Injector Beam Position Monitor Front-End Software Luciano Piccoli, Stephen Foulkes, Margaret Votava and Charles Briegel Fermi National Accelerator.
Short introduction Pulsar Parkes. Outline PDFB – Single beam pulsar timing system CASPER – Single beam pulsar coherent dedispersion system.
A real-time software backend for the GMRT : towards hybrid backends CASPER meeting Capetown 30th September 2009 Collaborators : Jayanta Roy (NCRA) Yashwant.
August 2003 At A Glance The IRC is a platform independent, extensible, and adaptive framework that provides robust, interactive, and distributed control.
Version 10.1 Xilinx Tools Update Terry Filiba CASPER Workshop II.
The Green Bank Telescope Frank Ghigo, National Radio Astronomy Observatory 7 th US VLBI Technical Meeting, Haystack, Nov 2009.
ATCA GPU Correlator Strawman Design ASTRONOMY AND SPACE SCIENCE Chris Phillips | LBA Lead Scientist 17 November 2015.
April 8/9, 2003 Green Bank GBT PTCS Conceptual Design Review John Ford September 28, 2009 Casper Instrumentation at Green Bank The NRAO is operated for.
Demonstrations of RDBE-PFB Data Flow. Review the original PFB Data Flow.
DDRIII BASED GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD PART B PRESENTATION STUDENTS: OLEG KORENEV EUGENE REZNIK SUPERVISOR: ROLF HILGENDORF 1 Semester:
Software tools for digital LLRF system integration at CERN 04/11/2015 LLRF15, Software tools2 Andy Butterworth Tom Levens, Andrey Pashnin, Anthony Rey.
The ALICE Data-Acquisition Read-out Receiver Card C. Soós et al. (for the ALICE collaboration) LECC September 2004, Boston.
FP7 Uniboard project Digital Receiver G. Comoretto, A. Russo, G. Tuccari, A Baudry, P. Camino, B. Quertier Dwingeloo, February 27, 2009.
Virtualization for Cloud Computing
CHAPTER 1: Computers and Systems
Mark 5 / VLBA Correlator Topics
The UniBoard Generic Hardware for Radio Astronomy Signal Processing
ENG3050 Embedded Reconfigurable Computing Systems
JIVE UniBoard Correlator (JUC) Firmware
05/08/09.
Commodity Flash ADC-FPGA Based Electronics for an
The performance requirements for DSP applications continue to grow and the traditional solutions do not adequately address this new challenge Paradigm.
The Uniboard  FPGA Processing for Astronomy
05/08/09.
Readout Systems Update
Presentation transcript:

April 8/9, 2003 Green Bank GBT PTCS Conceptual Design Review Ron DuPlain, Scott Ransom, Paul Demorest, Patrick Brandt, John Ford, Amy Shelton CASPER information courtesy of Terry Filiba and the CASPER group Launching GUPPI The NRAO is operated for the National Science Foundation (NSF) by Associated Universities, Inc. (AUI), under a cooperative agreement.

2 Outline CASPER – Center for Astronomical Signal Processing and Electronics Research GUPPI – The Green Bank Ultimate Pulsar Processing Instrument Control Software Design Results and Conclusions

3 CASPER Center for Astronomical Signal Processing and Electronics Research –The goal of CASPER is to streamline and reduce the current radio astronomy instrumentation design flow through the development of an open-source, platform-independent design approach. –This incorporates reconfigurable, modular, easily upgradeable hardware with standard, parameterized design libraries that abstract away the underlying details of the system. –Design simplifies to creation of block diagrams of components from standard libraries and the designer's brain. –

4 CASPER Tools Hardware and matching software support for matlab/simulink based design using Xilinx System Generator along with custom I/O blocksets and EDK firmware Supports Virtex-II Pro, soon to support Virtex-4 and -5 Hardware platforms include the iBOB, BEE2, and ADC boards to go with them. Reconfigurable Open Architecture Computing Hardware (ROACH) board, AKA Son of iBOB being brought up. Allows algorithm-level design by domain experts.

5 Polyphase Filter Banks

6 BEE2

7 IBOB and IADC

Another pulsar backend? We already have 5! GUPPI: 8-bit, 800MHz, 4096 chan, Full Stokes, and coherent dedisp BCPM: 4-bit, 48-96MHz, 96 chan, public Spectral Proc: 6-bit, <40MHz, 1024 chan, public Spigot: 3-level, 50/800MHz, 1024/2048 chan, public GASP: 8-bit, <100MHz, coherent dedisp, private CGSR2: 2-bit, <100MHz, coherent dedisp, private The only machines to give Full Stokes are GASP, CGSR2, and the Spectral Processor

GUPPI's Advantages Searching: 800MHz of BW, 4096 chan, and RFI-resistance (from polyphase filterbank) will make GUPPI a “Super- Spigot” that will be unbeatable for searches from 1-5 GHz (previously the BCPM and Spigot)‏ High Dynamic-Range Studies: 8-bit sampling, high spectral resolution and Full Stokes will make GUPPI perfect for scintillation studies, HI absorption, Faraday rotation measurements, polarization studies, and singlepulse studies (previously the Spectral Processor)‏ Ultra-High Precision Timing: 8-bit sampling, 800MHz of BW, and RFI resistance will allow unprecedented timing precision from 1-3 GHz for millisecond pulsars (i.e. the NANOGrav project and the search for nHz gravitational waves; previously GASP/CGSR2)‏

10 GUPPI History GBT Future Instrumentation Workshop, September 2006 University of Cincinnati Group worked on it until May, 2007, Produced report and basic design 2 WVU summer students and Glen Langston built “event capture” device over the summer Scott Ransom yells at us to “stop planning and get to work” in August, 2007 October 29th, 2007, Held workshop to brainstorm the project and get started on detailed design and implementation April 4th, first pulsar observation (under test conditions with 43m telescope)‏

11 Original UC design

12 GUPPI BEE2 signal processing chain Each 1.6 GS/s stream uses 1 FPGA for signal processing, 1 IBOB for data acquisition 4096 point PFB/FFT, with data streaming in and out, diagnostics in Block Ram Combines signals from each polarization, calculates stokes parameters, accumulates, and packages data, transmits over 10 Gb Ethernet to host. Minimum 50 microsecond accumulations ~ MB/sec data rate

13 GUPPI Software Design Software Requirements –Provide read and write access to all control parameters and monitor points –Start and Stop the data acquisition –Be compatible with, but independent of, the GBT M&C system Platform Requirements –Connections to the hardware modules –Defined interface to data acquisition software –Python interpreter on the host machine

Controller core logic parameter exposure Data Acquisition interface Data Acquisition data storage data quick look data status Server Controller access Client “external” interface Demux common parameter access fully qualify parameter names IBOB Interface parameter access (TinySH client)‏ (“Runs” on IBOB.)‏ BEE2 Interface parameter access (client-server)‏ (Runs on BEE2.)‏ The dashed box contains those modules which will run on GUPPI host, “beef.” Software Connections

15 User client module functions Simple command line interface Allows users to set and get all parameter values Allows users to start and stop FPGA processes Python based, extensible with standard Python functionality Users can write/run their own scripts to control observations Client modules can be seamlessly integrated into GBT M&C system, or any system that can open a connection to a Python SimpleXMLRPCServer

Hardware Parameters hardware design excerpt (right)‏ software register: BRAM:

GUPPI Command Prompt simple command prompt wrapped around Python interpreter tab completion for functions and parameter names four basic functions: –get and set for parameters –load and unload for FPGA profiles

Just add Python write simple scripts to build more functions e.g. use Python execfile import Python modules for extensibility e.g. matplotlib (pylab) for plotting

19 Data Acquisition Software Multi-threaded shared memory architecture C program Connects to 10 Gb Ethernet using UDP Buffers data, provides quick-look functions Streams data to disk in PSRFITS format Handles 300 MB/S data stream with Myricom 10 Gb Ethernet card, Tyan Motherboard, Opteron Processors and AMCC hardware RAID Interfaces to Python based controller through shared memory command buffer

20 Portability and Extensibility Controller written in Python Data Acquisition software written in C Host is 64 bit Linux system, BEE2 runs 32 bit Linux system All connections to hardware are portable to newer/different interfaces All code written by NRAO staff GPL licensed

21 First Light

22 GUPPI Future Directions Add more diagnostics Add other configurations, narrow bandwidths, more channels, wider/narrower outputs, etc. Add coherent dedispersion modes –Long FFT's needed to implement inverse ISM filter –Possibly brute force better? Using convolution instead of FFT- >Multiply->IFFT –Maybe better to stream out to computers for calculations. Make it robust enough to release for everyday use –Integrate with GBT observing system

23 Conclusions Reconfigurable Computing platforms make for quick hardware development –GUPPI started in earnest in October, First light was in April Standard software interfaces make for quick control interface development –The BEE2 and IBOB platforms use a common shell interface to the FPGA parameter space, allowing for easy portability between all hardware subsystems –Python for the development language allowed the power of the Python interpreter to be used to provide complex functions easily

24 Further Information For more information: – – or other

25 The End