Lecture 13 A/D Converter & D/A Converter

Outline Basic Operation Single Scan Mode Continuous Scan Mode Group Scan Mode Interrupt Sources Registers D/A Converter

Overview The RX210 Group includes a 12-bit successive approximation A/D converter Up to 16 channel analog inputs, temperature sensor outputs, or internal reference voltages can be selected Converter converts a maximum of 16 selected channels of analog inputs, temperature sensor outputs, or internal reference voltages into a 12-bit digital value through successive approximation The A/D converter has three operating modes Single scan mode The analog inputs of up to 16 arbitrarily selected channels are converted for only once in ascending channel order Continuous scan mode The analog inputs of up to 16 arbitrarily selected channels are continuously converted in ascending channel order Group scan mode Up to 16 channels of the analog inputs are arbitrarily divided into two groups and converted in ascending channel order in each group

Overview (cont.) Group A and group B In group scan mode, the scan start conditions of group A and group B can be independently selected Allowing A/D conversion of group A and group B to be started independently In double trigger mode One arbitrarily selected analog input channel is converted in single scan mode or group scan mode (group A) The resulting data of A/D conversion started by the first and second triggers are stored into separate registers Duplication of A/D conversion data Self-diagnosis is executed once at the beginning of each scan One of the three voltages internally generated in the 12-bit A/D converter is converted A/D conversion of the temperature sensor output or the internal reference voltage is accomplished independently

Scanning Operation A/D conversion is performed sequentially on the analog inputs of the specified channels In continuous scan mode, one or more specified channels are scanned repeatedly Until the ADST bit in ADCSR is cleared to 0 from 1 by software In group scan mode, the selected channels of group A and the selected channels of group B are scanned once After starting to be scanned according to the respective triggers In single scan mode and continuous scan mode, A/D conversion is performed for ANn channels selected By the ADANSA register, starting from the channel with the smallest number n In group scan mode, A/D conversion is performed for ANn channels of group A and group B selected By the ADANSA and ADANSB registers, respectively, starting from the channel with the smallest number n

Scanning Operation (cont.) When the temperature sensor output or the internal reference voltage is selected Single scan mode should be used for A/D conversion Double trigger mode is to be used with single scan mode or group scan mode A/D conversion data of a channel selected by the DBLANS[4:0] bits in ADCSR is duplicated Only if the conversion is started by any of the MTU or ELC (Event Link Controller) triggers selected by TRSA[3:0] bits in ADSTRGR ELC connects (links) the events generated by various peripheral modules to different modules When any of AN000 to AN002 channels is set by the SHANS[2:0] bits in ADSHCR The channel uses a channel-dedicated sample-and-hold circuit The set analog input is sampled and held before the first A/D conversion of each scan

Single Scan Mode Basic operation with channel-dedicated sample-and-hold circuits not used A/D conversion is performed once on the analog input of the specified channels Temperature sensor output A/D conversion select bit (TSS) and internal reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection) A/D conversion is performed for ANn channels selected by the ADANSA register When the ADST bit in ADCSR is set to 1 (A/D conversion start) by software, synchronous trigger (MTU or ELC), or asynchronous trigger input Each time A/D conversion of a single channel is completed The A/D conversion result is stored into the corresponding A/D data register (ADDRy) When A/D conversion of all the selected channels is completed An S12ADI0 interrupt request is generated If the ADIE bit in ADCSR is 1 (interrupt upon scanning completion)

Single Scan Mode (cont.) The ADST bit remains 1 (A/D conversion start) during A/D conversion Automatically cleared to 0 when A/D conversion of all the selected channels is completed The 12-bit A/D converter enters a wait state

Single Scan Mode (cont.) Basic operation with channel-dedicated sample-and-hold circuits used Sample-and-hold operation is first performed Then A/D conversion is performed once on the analog input of all the selected channels The channels whose channel-dedicated sample-and-hold circuit is to be used can be selected by SHANS[2:0] bits in ADSHCR Temperature sensor output A/D conversion select bit (TSS) and internal reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection) Analog input sampling of all the channels whose channel- dedicated sample-and-hold circuit is to be used is started When the ADST bit in ADCSR is set to 1 (A/D conversion start) by software, synchronous trigger (MTU or ELC), or asynchronous trigger input After sample-and-hold operation, A/D conversion is performed for ANn channels selected by the ADANSA register

Single Scan Mode (cont.) Starting from the channel with the smallest number n Each time A/D conversion of a single channel is completed The A/D conversion result is stored into the corresponding A/D data register (ADDRy) When A/D conversion of all the selected channels is completed An S12ADI0 interrupt request is generated If the ADIE bit in ADCSR is 1 (interrupt upon scanning completion) The ADST bit remains 1 (A/D conversion start) during A/D conversion Automatically cleared to 0 when A/D conversion of all the selected channels is completed The 12-bit A/D converter enters a wait state

Single Scan Mode (cont.) Example of operation in single scan mode Channel-dedicated sample-and-hold circuits used Basic operation: AN000 to AN002 selected

Single Scan Mode (cont.) Channels selection and self-diagnosis (channel-dedicated sample-and-hold circuits not used) A/D conversion is first performed for the self-diagnosis voltage VREFH0 × 0, VREFH0 × 1/2, or VREFH0 × 1 generated from the reference power supply voltage (VREFH0) supplied to the 12-bit A/D converter A/D conversion is performed once on the analog input of the selected channels Temperature sensor output A/D conversion select bit (TSS) and internal reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection) A/D conversion for self-diagnosis is first started When the ADST bit in ADCSR is set to 1 (A/D conversion start) by software, synchronous trigger (MTU or ELC), or asynchronous trigger input When A/D conversion for self-diagnosis is completed The A/D conversion result is stored into the A/D self-diagnosis data register (ADRD)

Single Scan Mode (cont.) A/D conversion is then performed for ANn channels selected by the ADANSA register Starting from the channel with the smallest number n Each time A/D conversion of a single channel is completed The A/D conversion result is stored into the corresponding A/D data register (ADDRy) When A/D conversion of all the selected channels is completed An S12ADI0 interrupt request is generated if the ADIE bit in ADCSR is 1 (S12ADI0 interrupt upon scanning completion enabled) The ADST bit remains 1 (A/D conversion start) during conversion Automatically cleared to 0 when A/D conversion of all the selected channels is completed The 12-bit A/D converter enters a wait state

Single Scan Mode (cont.) Example of operation in single scan mode Basic operation + self-diagnosis

Single Scan Mode (cont.) Channels selection and self-diagnosis (channel-dedicated sample-and-hold circuits used) Sample-and-hold operation is first performed A/D conversion is performed once for the self-diagnosis voltage VREFH0 × 0, VREFH0 × 1/2, or VREFH0 × 1 generated from the reference power supply voltage (VREFH0) supplied to the 12-bit A/D converter A/D conversion is performed only once on the analog input of the selected channels Temperature sensor output A/D conversion select bit (TSS) and internal reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection) Analog input sampling of all the channels whose channel- dedicated sample-and-hold circuit is to be used is started When the ADST bit in ADCSR is set to 1 (A/D conversion start) by software, synchronous trigger (MTU or ELC), or asynchronous trigger input

Single Scan Mode (cont.) After sample-and-hold operation, A/D conversion for self- diagnosis is started When A/D conversion for self-diagnosis is completed The A/D conversion result is stored into the A/D self-diagnosis data register (ADRD) A/D conversion is then performed for ANn channels selected by the ADANSA register Starting from the channel with the smallest number n Each time A/D conversion of a single channel is completed The A/D conversion result is stored into the corresponding A/D data register (ADDRy) When A/D conversion of all the selected channels is completed An S12ADI0 interrupt request is generated if the ADIE bit in ADCSR is 1 (S12ADI0 interrupt upon scanning completion enabled) The ADST bit remains 1 during A/D conversion Automatically cleared to 0 as conversion of all channels is finished Then the 12-bit A/D converter enters a wait state

Single Scan Mode (cont.) Example of operation in single scan mode Channel-dedicated sample-and-hold circuits used + self- diagnosis

Single Scan Mode (cont.) A/D conversion of the temperature sensor output Should be performed in single scan mode All the channels should be deselected Set the ANSA[15:0] bits in ADANSA to 0000h and DBLE bit in ADCSR to 0 Self-diagnosis should be deselected The internal reference voltage A/D conversion select bit (OCS) in ADEXICR should also be set to 0 (non-selection) A/D conversion is started for the temperature sensor output When the ADST bit in ADCSR is set to 1 (A/D conversion start) by the trigger from the temperature sensor When A/D conversion is completed The A/D conversion result is stored into the A/D temperature sensor data register (ADTSDR) If the ADIE bit in ADCSR is 1 (S12ADI0 interrupt upon scanning completion enabled), an S12ADI0 interrupt request is generated The ADST bit remains 1 during A/D conversion

Single Scan Mode (cont.) Automatically cleared to 0 when A/D conversion is completed Then the 12-bit A/D converter enters a wait state

Single Scan Mode (cont.) A/D conversion of the internal reference voltage Should be performed in single scan mode All the channels should be deselected Set the ANSA[15:0] bits in ADANSA to 0000h and DBLE bit in ADCSR to 0 Self-diagnosis should be deselected The temperature sensor output A/D conversion select bit (TSS) in ADEXICR should also be set to 0 (non-selection) A/D conversion is started for the internal reference voltage When the ADST bit in ADCSR is set to 1 (A/D conversion start) by software, the synchronous trigger (MTU or ELC), or the asynchronous trigger input When A/D conversion is completed The A/D conversion result is stored into the A/D internal reference voltage data register (ADOCDR) If the ADIE bit in ADCSR is 1 (S12ADI0 interrupt upon scanning completion enabled), an S12ADI0 interrupt request is generated

Single Scan Mode (cont.) The ADST bit remains 1 during A/D conversion Automatically cleared to 0 when A/D conversion is completed Then the 12-bit A/D converter enters a wait state

Single Scan Mode (cont.) In single scan mode with double trigger mode Single scan operation started by the MTU or ELC trigger is performed twice Self-diagnosis should be deselected The temperature sensor output A/D conversion select bit (TSS) and internal reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection) Duplication of A/D conversion data is enabled By setting the channel numbers to be duplicated to the DBLANS[4:0] bits in ADCSR Setting the DBLE bit in ADCSR to 1 When the DBLE bit in ADCSR is set to 1, channel selection using the ADANSA register is invalid MTU or ELC triggers should be selected using the TRSA[3:0] bits in ADSTRGR The EXTRG bit and TRGE bit in ADCSR should be set to 0 and 1, respectively Software trigger should not be used

Single Scan Mode (cont.) A/D conversion is started on the single channel selected by the DBLANS[4:0] bits in ADCSR When the ADST bit in ADCSR is set to 1 (A/D conversion start) by the MTU or ELC trigger input When A/D conversion is completed The A/D conversion result is stored into the corresponding A/D data register (ADDRy) The ADST bit is automatically cleared to 0 The 12-bit A/D converter enters a wait state An S12ADI0 interrupt request is not generated irrespective of the ADIE (interrupt upon scanning completion) bit setting in ADCSR When the ADST bit in ADCSR is set to 1 (A/D conversion start) by the second trigger input A/D conversion is started on the single channel selected by the DBLANS[4:0] bits in ADCSR When A/D conversion is completed The A/D conversion result is stored into the A/D data duplication register (ADDBLDR)

Single Scan Mode (cont.) Exclusively used in double trigger mode If the ADIE bit in ADCSR is 1, an interrupt request is generated The ADST bit remains 1 (A/D conversion start) during A/D conversion Automatically cleared to 0 when A/D conversion is completed Then the 12-bit A/D converter enters a wait state

Continuous Scan Mode A/D conversion is performed repeatedly on the analog input of the specified channel The temperature sensor output A/D conversion select bit (TSS) and internal reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection) The 12-bit A/D converter sequentially starts A/D conversion for ANn channels selected by the ADANSA register When the ADST bit in ADCSR is set to 1 (A/D conversion start) by software, synchronous trigger (MTU or ELC), or asynchronous trigger input Starting from the channel with the smallest number n Each time A/D conversion of a single channel is completed The A/D conversion result is stored into the corresponding A/D data register (ADDRy) When A/D conversion of all the selected channels is completed An S12ADI0 interrupt request is generated if the ADIE bit in ADCSR is 1 (S12ADI0 interrupt upon scanning completion enabled)

Continuous Scan Mode (cont.) The ADST bit in ADCSR is not automatically cleared to 0 The above steps 2 and 3 are repeated as long as the bit remains 1 (A/D conversion start) When the ADST bit in ADCSR is set to 0 (A/D conversion stop), A/D conversion stops The 12-bit A/D converter enters a wait state When the ADST bit is later set to 1 (A/D conversion start) A/D conversion is started again for ANn channels selected by the ADANSA register Starting from the channel with the smallest number n

Continuous Scan Mode (cont.) Example of operation in continuous scan mode Basic operation: AN000 to AN002 selected

Continuous Scan Mode (cont.) When the channel-dedicated sample-and-hold circuit is used Sample-and-hold operation is first performed Then A/D conversion is repeated on the analog input of all the selected channels The channels whose channel-dedicated sample-and-hold circuit is to be used can be selected by the SHANS[2:0] bits in ADSHCR Temperature sensor output A/D conversion select bit (TSS) and internal reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection) Analog input sampling of all the channels whose channel- dedicated sample-and-hold circuit is to be used is started When the ADST bit in ADCSR is set to 1 (A/D conversion start) by software or synchronous trigger (MTU or ELC) input After sample-and-hold operation, A/D conversion is performed for ANn channels selected by the ADANSA register Starting from the channel with the smallest number n Each time A/D conversion of a single channel is completed

Continuous Scan Mode (cont.) The A/D conversion result is stored into the corresponding A/D data register (ADDRy) When A/D conversion of all the selected channels is completed An S12ADI0 interrupt request is generated if the ADIE bit in ADCSR is 1 (S12ADI0 interrupt upon scanning completion enabled) At the same time, analog input sampling is started for all the channels whose channel-dedicated sample-and-hold circuit is to be used The ADST bit is not automatically cleared to 0 The above steps are repeated as long as the bit remains 1 When the ADST bit is set to 0 (A/D conversion stop) A/D conversion stops The 12-bit A/D converter enters a wait state When the ADST bit is later set to 1 (A/D conversion start) Analog input sampling is started again for all the channels whose channel-dedicated sample-and-hold circuit is to be used

Continuous Scan Mode (cont.) Example of operation in continuous scan mode Channel-dedicated sample-and-hold circuit is used

Continuous Scan Mode (cont.) Channels selection and self-diagnosis A/D conversion is first performed for the self-diagnosis voltage VREFH0 × 0, VREFH0 × 1/2, or VREFH0 × 1 generated from the reference power supply voltage (VREFH0) supplied to the 12-bit A/D converter Then A/D conversion is performed on the analog input of the selected channels The temperature sensor output A/D conversion select bit (TSS) and internal reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection) A/D conversion for self-diagnosis is first started When the ADST bit in ADCSR is set to 1 (A/D conversion start) by software, synchronous trigger (MTU or ELC), or asynchronous trigger input When A/D conversion for self-diagnosis is completed The A/D conversion result is stored into the A/D self-diagnosis data register (ADRD)

Continuous Scan Mode (cont.) A/D conversion is then performed for ANn channels selected by the ADANSA register Starting from the channel with the smallest number n Each time A/D conversion of a single channel is completed The A/D conversion result is stored into the corresponding A/D data register (ADDRy) When A/D conversion of all the selected channels is completed An S12ADI0 interrupt request is generated if the ADIE bit in ADCSR is 1 (S12ADI0 interrupt upon scanning completion enabled) At the same time, the 12-bit A/D converter starts A/D conversion for self-diagnosis Then starts A/D conversion on ANn channels selected by the ADANSA register The ADST bit is not automatically cleared to 0 The above steps are repeated as long as the bit remains 1 When the ADST bit is set to 0 (A/D conversion stop), A/D conversion stops The 12-bit A/D converter enters a wait state

Continuous Scan Mode (cont.) When the ADST bit is later set to 1 (A/D conversion start) The A/D conversion for self-diagnosis is started again Example of operation in continuous scan mode Basic operation + self-diagnosis

Continuous Scan Mode (cont.) Channels selection and self-diagnosis and self-diagnosis Sample-and-hold operation is first performed Then A/D conversion is performed for the self-diagnosis voltage VREFH0 × 0, VREFH0 × 1/2, or VREFH0 × 1 generated from the reference power supply voltage (VREFH0) supplied to the 12-bit A/D converter After that, A/D conversion is performed on the analog input of the selected channels Temperature sensor output A/D conversion select bit (TSS) and internal reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection) Analog input sampling of all the channels whose channel- dedicated sample-and-hold circuit is to be used is started When the ADST bit in ADCSR is set to 1 (A/D conversion start) by software, synchronous trigger (MTU or ELC), or asynchronous trigger input After sample-and-hold operation, A/D conversion for self- diagnosis is started

Continuous Scan Mode (cont.) When A/D conversion for self-diagnosis is completed The A/D conversion result is stored into the A/D self-diagnosis data register (ADRD) A/D conversion is then performed for ANn channels selected by the ADANSA register Starting from the channel with the smallest number n Each time A/D conversion of a single channel is completed The A/D conversion result is stored into the corresponding A/D data register (ADDRy) When A/D conversion of all the selected channels is completed An S12ADI0 interrupt request is generated if the ADIE bit in ADCSR is 1 (S12ADI0 interrupt upon scanning completion enabled) At the same time, analog input sampling is started for all the channels whose channel-dedicated sample-and-hold circuit is to be used The ADST bit is not automatically cleared to 0 The above steps are repeated as long as the bit remains 1

Continuous Scan Mode (cont.) When the ADST bit is set to 0 (A/D conversion stop) A/D conversion stops The 12-bit A/D converter enters a wait state When the ADST bit is later set to 1 (A/D conversion start) Analog input sampling is started again for all the channels whose channel-dedicated sample-and-hold circuit is to be used Example of operation in continuous scan mode Channel-dedicated sample-and-hold circuit + self-diagnosis

Group Scan Mode A/D conversion is performed once on the analog inputs of all the specified channels in group A and group B After scanning is started by the MTU or ELC trigger Scan operation of each group is similar to the scan operation in single scan mode The group A trigger and group B trigger can be selected using the TRSA[3:0] and TRSB[3:0] bits in ADSTRGR, respectively The different triggers should be used for group A and group B to prevent simultaneous A/D conversion of group A and group B Software trigger should not be used The group A and group B channels to be converted are selected using the ADANSA register and ADANSB register, respectively Group A and group B cannot use the same channels The temperature sensor output A/D conversion select bit (TSS) and internal reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection) When self-diagnosis is selected in group scan mode

Group Scan Mode (cont.) Self-diagnosis is separately executed for group A and group B An operation in group scan mode using a trigger from the MTU Scanning of group A is started by the TRG4AN trigger from MTU When group A scanning is completed An S12ADI0 interrupt is output if the ADIE bit in ADCSR is 1 Scanning of group B is started by the TRG4BN trigger from MTU When group B scanning is completed A GBADI interrupt is output if the GBADIE bit in ADCSR is 1

Group Scan Mode (cont.) In group scan mode with double trigger mode Single scan operation started by the MTU or ELC trigger is performed twice for group A For group B, single scan operation started by the MTU or ELC trigger is performed once The group A trigger and group B trigger can be selected using the TRSA[3:0] and TRSB[3:0] bits in ADSTRGR, respectively The different triggers should be used for group A and group B to prevent simultaneous A/D conversion of group A and group B Software trigger, synchronous trigger (temperature sensor), or asynchronous trigger (ADTRG0#) should not be used The group A and group B channels to be A/D-converted are selected using the DBLANS[4:0] bits in ADCSR register and ADANSB register, respectively The same channels cannot be selected for both groups In group scan mode, the temperature sensor output A/D conversion select bit (TSS) and internal reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection)

Group Scan Mode (cont.) Self-diagnosis cannot be selected Duplication of A/D conversion data is enabled By setting the channel numbers to be duplicated to the DBLANS[4:0] bits in ADCSR and setting the DBLE bit in ADCSR to 1 An operation in group scan mode with double trigger mode using a trigger from the MTU Scanning of group B is started by the TRG0AN trigger from MTU When group B scanning is completed A GBADI interrupt is output if the GBADIE bit in ADCSR is 1 The first scanning of group A is started by the first TRG4ABN trigger from the MTU When the first scanning of group A is completed The conversion result is stored into ADDRy An S12ADI0 interrupt request is not generated irrespective of the ADIE bit setting in ADCSR The second scanning of group A is started by the second TRG4ABN trigger from the MTU

Group Scan Mode (cont.) When the second scanning of group A is completed The conversion result is stored into ADDBLDR An S12ADI0 interrupt is output if the ADIE bit is 1

Automatic Register Clearing Function Setting the ACE bit in ADCER to 1 automatically clears the A/D data registers to 0000h When the A/D data registers are read by the CPU, DTC, or DMAC ADDRy, ADRD, ADTSDR, and ADOCDR Enables detection of update failures of the A/D data registers An examples in which the function to automatically clear the ADDRy register is enabled and disabled When the ACE bit in ADCER is 0 (automatic clearing is disabled) If the A/D conversion result (0222h) is not written to the ADDRy register for some reason The old data (0111h) will be the ADDRy value If this ADDRy value is written to a general register using an A/D scan end interrupt The old data (0111h) can be saved in the general register When checking whether there is an update failure

Automatic Register Clearing Function (cont.) It is necessary to frequently save the old data in the RAM or a general register When the ACE bit in ADCER is 1 (automatic clearing is enabled) If ADDRy = 0111h is read by the CPU, DTC, or DMAC, ADDRy is automatically cleared to 0000h If the new A/D conversion result 0222h cannot be transferred to ADDRy for some reason The cleared data (0000h) remains as the ADDRy value If this ADDRy value is read into a general register using an A/D scan end interrupt at this point 0000h will be saved in the general register Occurrence of an ADDRy update failure can be determined by simply checking that the read data value is 0000h

A/D-Converted Value Addition Function The same channel is A/D converted two to four consecutive times The sum of the converted values is stored in the data register The use of the average of these results can improve the accuracy of A/D conversion Depending on the types of noise components that are present Cannot always guarantee an improvement in A/D conversion accuracy A/D-converted value addition function can be used For channel-selected analog input A/D conversion and internal reference voltage A/D conversion

Asynchronous Triggers The A/D conversion can be started by the input of an asynchronous trigge The A/D conversion start trigger select bits (ADSTRGR.TRSA[3:0]) should be set to 0000b A high-level signal should be input to the asynchronous trigger ADTRG0# pin The ADCSR.TRGE and ADCSR.EXTRG bits should be set to 1

Synchronous Triggers The A/D conversion can be started by a synchronous trigger of the MTU, TPU, ELC, or temperature sensor The ADCSR.TRGE bit should be set to 1 The ADCSR.EXTRG bit should be cleared to 0 The relevant source should be selected by ADSTRGR.TRSA[3:0] and TRSB[3:0] bits When the temperature sensor output is converted A trigger from the temperature sensor should be used to start the A/D conversion A trigger from the temperature sensor cannot be used when an analog input channel or the internal reference voltage is converted

Interrupt Sources The 12-bit A/D converter can send scan end interrupt requests S12ADI0 and GBADI to the CPU Setting the ADIE bit in ADCSR to 1 and 0 enables and disables an S12ADI0 interrupt, respectively Setting the GBADIE bit in ADCSR to 1 and 0 enables and disables a GBADI interrupt, respectively The DTC or DMAC can be started up when an S12ADI0 or a GBADI interrupt is generated Using an interrupt to allow the DTC or DMAC to read the converted data enables continuous conversion without burden on software The ELC connects the S12ADI0 interrupt request signal to the predetermined module as the event signal i.e., event linkage The GBADI interrupt request cannot be used as the event signal The event signal can be output Irrespective of the setting of the corresponding interrupt request enable bit

Interrupt Sources (cont.) The 12-bit A/D converter outputs the A/D conversion end event The 12-bit A/D converter can be started by the predetermined event by setting ELSRn of the ELC When an event occurs during A/D conversion, it is invalid

Registers A/D Control Register (ADCSR)

Registers (cont.) A/D Control Extended Register (ADCER)

Registers (cont.) A/D Channel Select Register A (ADANSA) A/D Channel Select Register B (ADANSB)

Registers (cont.) A/D Sample and Hold Circuit Control Register (ADSHCR)

Registers (cont.) A/D Conversion Extended Input Control Register (ADEXICR)

Registers (cont.) A/D Data Registers y (ADDRy) (y = 0 to 15) ADCER.ADRFMT = 0 (Setting for right-alignment) ADCER.ADRFMT = 1 (Setting for left-alignment) When A/D-converted value addition mode is selected

Registers (cont.) A/D Data Duplication Register (ADDBLDR) ADDBLDR ADCER.ADRFMT = 0 (Setting for right-alignment) ADCER.ADRFMT = 1 (Setting for left-alignment) When A/D-converted value addition mode is selected

Registers (cont.) A/D Self-Diagnosis Data Register (ADRD) ADCER.ADRFMT = 0 (Setting for right-alignment) ADCER.ADRFMT = 1 (Setting for left-alignment)

Registers (cont.) A/D Temperature Sensor Data Register (ADTSDR) ADCER.ADRFMT = 0 (Setting for right-alignment) ADCER.ADRFMT = 1 (Setting for left-alignment)

Registers (cont.) A/D Internal Reference Voltage Data Register (ADOCDR) ADCER.ADRFMT = 0 (Setting for right-alignment) ADCER.ADRFMT = 1 (Setting for left-alignment)

Registers (cont.) A/D Start Trigger Select Register (ADSTRGR)

D/A Converter The specifications of the D/A converter Resolution: 10 bits Output channels: Two channels Low power consumption function: Module stop state can be set for each unit Event link function (input) D/A0 conversion can be started when an event signal is input Pin Configuration of D/A Converter

D/A Converter (cont.)

Operation The D/A converter includes D/A conversion circuits for two channels Each of which can operate independently D/A converter is enabled and the conversion result is output When the DAOEi bit (i = 0, 1) in DACR is set to 1 An operation example of D/A conversion on channel 0 Write the data for conversion to DADR0 Set the DAOE0 bit in DACR to 1 to start D/A conversion The conversion result is output from the analog output pin DA0 after the conversion time tDCONV has elapsed The conversion result continues to be output until DADR0 is written to again Or the DAOE0 bit is cleared to 0 The output value is expressed by the following formula:

Operation (cont.) If DADR0 is written to again, the conversion is immediately started The conversion result is output after the conversion time tDCONV has elapsed If the DAOE0 bit is cleared to 0, analog output is disabled

Registers D/A Data Register m (DADRm) (m = 0, 1) DADRm Format Select Register (DADPR)

Registers (cont.) D/A Control Register (DACR)