PERFORMANCE COMPARISON AND EVALUATION OF A AND ITS IMPLEMENTATION IN RECONFIGURABLE ENVIRONMENT SABA ZIA 2007-NUST-MS-PHD-TE-05 Project Advisor: Dr. N. D Gohar (HOD CSE, SEECS, NUST) Committee Members: Mr. Imtiaz Khokhar (Asst. Prof, EE, MCS, NUST) Dr. Adnan Khan (Asst. Prof, EE, MCS, NUST) Mr. Bilal Saqib (lecturer, CSE, SEECS, NUST)

Outline  Introduction  SDR, OFDM based standards, WLAN  Reconfigurable Environment  Performance Evaluation in a Reconfigurable Environment  Reconfigurable Kernels  Implementation Overview  Kernel Algorithm  Kernel Simulation Results  Kernel Synthesis: Max Frequency, Area requirements  Simulated and Synthesized Example  WLAN PHY (802.11a) 2

Introduction 3

 Performance Comparison and Evaluation of a and its Implementation in a Reconfigurable Environment  Software Defined Radio Development using a Network-On-Chip based Rapid Prototyping Platform 4 Radio Frequency (RF) Radio Frequency (RF) Analog to Digital Conversion (A/D) Analog to Digital Conversion (A/D) Baseband Processing Control (Parameterization) Transmit Receive RF Front End

5 Physical Layer Architecture and Kernel Identification (802.11a) Ref: IEEE Std a-1999(R2003)

6 Physical Layer Architecture and Kernel Identification Data Scrambler/ Descrambler Convolutional Encoder / Viterbi decoder Data interleaver/ De-interleaver Guard interval insertion/ Removal OFDM modulation IFFT/FFT OFDM modulation IFFT/FFT Subcarrier Modulation Mapping/ De- mapping Puncturing / De- puncturing Point Arrangement Bit Reversal

Individual Properties of each Kernel Data Scrambler/Descrambler 7  S (x)=x 7 +x 4 +1 Ref: IEEE Std a-1999(R2003)

Individual Properties of each Kernel Convolutional Encoder/ Viterbi Decoder 8  R = ½, 2/3, ¾  For R= 1/2, G 0 =133 8 G 1 =  Decoding by Viterbi Algorithm Ref: IEEE Std a-1999(R2003)

Individual Properties of each Kernel Puncturing/De-puncturing Patterns 9 Ref: IEEE Std a-1999(R2003)

Individual Properties of each Kernel Data Interleaver/ De-interleaver  Block size corresponding to the number of bits in a single OFDM symbol, NCBPS  Two-step permutation  i = (N CBPS /16) (k mod 16) + floor(k/16) where k = 0,1,…,N CBPS – 1  j = s × floor (i/ s) + (i + N CBPS – floor(16 × i/N CBPS )) mod s where i = 0,1,… N CBPS – 1  The value of s is determined by the number of coded bits per subcarrier, N BPSC, according to s = max(N BPSC /2,1) 10

Individual Properties of each Kernel Subcarrier Modulation Mapping  BPSK,QPSK,16 QAM or 64 QAM depending on the rate requested  Gray coded constellation mappings  Resultant, d = (I + jQ) X K MOD 11 Ref: IEEE Std a-1999(R2003)

Individual Properties of each Kernel OFDM modulation (IFFT)  Divide the complex number string into groups of 48 complex numbers. Each such group will be associated with one OFDM symbol.  Each complex number is mapped into OFDM subcarriers numbered –26 to –22, –20 to –8, –6 to –1, 1 to 6, 8 to 20, and 22 to 26.  The “0” subcarrier, associated with center frequency, is omitted and filled with zero value.  Four subcarriers are inserted as pilots into positions –21, –7, 7, and 21. The total number of the subcarriers is 52 (48 + 4).  For each group of subcarriers –26 to 26, convert the subcarriers to time domain using inverse Fourier transform 12

Individual Properties of each Kernel OFDM modulation (FFT-DIT) 13 Ref: IEEE Std a-1999(R2003) j -j j -j W0W0 W1W1 W2W2 W3W3 W4W4 W5W5 W6W6 W7W7 Time Domain Samples Frequency Domain Outputs

Individual Properties of each Kernel Guard Interval Insertion  Prepend to the Fourier-transformed waveform a circular extension of itself thus forming a GI, and truncate the resulting periodic waveform to a single OFDM symbol length by applying time domain windowing. 14 Ref: IEEE Std a-1999(R2003)

Rate Dependent Parameters 15 Ref: IEEE Std a-1999(R2003)

Reconfigurable Environment 16

Reconfigurable Environment 17 System on Chip (SoC) Putting all the functions of a complete system (processor, memory, analog functions, external interfaces, timers, counters, voltage regulators, etc.) all on a single silicon chip, enabling the chip to operate as a standalone system

Communication Structures in System-on- Chip 18 Bus based Architecture µP Memory RF DSPKeyboard Point to Point Links µP Memory RF DSP Keyboard Network based Connections µPMemoryRF DSPKeyboard

Reconfigurable Environment 19 Network on Chip (NOC) Resource Router or Switch RNI

Reconfigurable Kernels 20  Algorithmic size functionality  Reused across several standards  Combined Spatially or Temporally for bigger dimension  Fulfills overall performance constraints of multiple standards

SDR supporting OFDM based wireless Standards 21

Role of Kernel and a in SDR  a is an OFDM based standard  Each individual block of the a at physical layer will serve the functionality of the basic kernel of OFDM block  Kernel would be expanded spatially or temporally  Implementation allows reconfiguration to meet the constraints of other wireless standards 22

Performance Evaluation in Reconfigurable Environment  Size  Performance  Cost  Power 23 Power Performance Cost Area

WLAN TX Controller  Initialization signals for datapath  Scrambler  Convolutional Encoder  Interleaver  Modulation Mapper  Point Arrange  FFT  Bit Reversal  Guard Insertion  State Machine  Short Preamble  Long Preamble  Header  Data  Initialization Signals for Controller WLAN TX CONTROLLER WLAN TX DATAPATH 24

Simulated and Synthesized Datapath IEEE STD a 25

Synthesis Results ScramblerScrambler start rst din clk dout KernelSlices XC4VSX25 Max Frequency (MHz) XC4VSX25 Scrambler5505

Simulation Results Scrambler/ Descrambler

Synthesis Results Convolutional Encoder clk Punc_en rst start Start puncture Encoding clk rst dout Encoding Puncturing din clk rst out rate Start puncture dout Puncturing

Synthesis Results Convolutional Encoder 29 ParameterXilinx Logic Corev6.0 XCV4-10 Designed Kernel XCV4-10 Area (slices)3214 Maximum Clock Frequency (MHz) (512 MHz XC4VSX25)

Simulation Results Convolutional Encoder with Puncturing

Synthesis Results Interleaver Ncbps Change Ncbps clk Serial_in Start First Permutation Addrb_0 Addrb_1 Permuted data1_0 Permuted data1_1 Ncbps Change Ncbps clk Permute d data_2 Start Second Permutation Addra_0 Addra_1 Permuted data1_0 Permuted data1_1 addra addrb clk dinb   douta addra addrb clk dinb douta

Synthesis Results Interleaver KernelSlices XC4VSX25 Max Frequency (MHz) XC4VSX25 Interleaver633188

Simulation Results Interleaver

Synthesis Results Modulation Mapper Data_from_mem_bpsk Data_from_mem_qpsk Data_from_mem_16QAM Data_from_mem_64QAM Modulation 64QAM_input 16QAM_input Bpsk_input Qpsk_input clk rst Start Imaginary_data Real_data Mem_addr_bpsk Mem_addr_qpsk Mem_addr_16QAM Mem_addr_64QAM addr clk dout addr clk dout addr clk dout addr clk dout

Synthesis Results Modulation Mapper KernelSlices XC4VSX25 Max Frequency (MHz) XC4VSX25 Modulation Mapper65275

Simulation Results Modulation Mapper

FFT-DIF State Machine

Synthesis Results FFT-DIF W nk Factor LUT Dual Port RAM Port A Dual Port RAM Port A Stage and Butterfly Controller + Data Memory Controller + Twiddle Memory Controller Stage and Butterfly Controller + Data Memory Controller + Twiddle Memory Controller Dual Port RAM Port B Dual Port RAM Port B Radix-2 Cell W nk

Comparison of Synthesis Results FFT-DIF Platform TSMC 90nm standard cell Area mm 2 Clock MHz Power mW Morphable Data Unit Reconfigurable Kernel Ref: M. Ali Shami, A Hemani “Morphable datapath Unit: Smart and efficient datapath for Signal Processing Applications”, 2008

Simulation Results FFT-DIF

Simulated and Synthesized Controller IEEE STD a 43

Pipelined Data Flow Short Preamble Long Preamble HeaderServiceData Kernel FFT Convolutional Encoder Scrambler Interleaver Modulation Mapper Point arrangement Bit Reversal Guard Insertion 128 clocks 2 clocks 48 clocks 172 clocks 4 clocks 151 clocks 66 clocks

Controller Review 46

Conclusion  NOC based radio prototyping platform  Flexibility and scalability of FPGAs  Performance of ASICs  Paper submitted in conference IEEE INFOCOM, 2010 titled “Reconfigurable FFT Kernel for Network on Chip based Radio System Prototyping Platform ” 47

Questions 48