An automatic tool flow for the combined implementation of multi-mode circuits Brahim Al Farisi, Karel Bruneel, João Cardoso, Dirk Stroobandt

Overview 1 Multi-mode circuit FPGA Dynamic reconfiguration: Modular dynamic reconfiguration (MDR) Dynamic circuit specialization (DCS) Novel tool flow Experiments and results Conclusions Future work

Multi-mode circuit 2 Several circuits, called modes, that are used mutually exclusive in time Example: software defined radio Goal: Area efficient implementation through hardware resource sharing

FPGA 3 FF LUTLUT

Conventional FPGA tool flow 4 Input: textual description of functionality SYNTHESIS MAP PLACE HDL design Configuration ROUTE LUT circuit

entity multiplexer is port( sel : in std_logic_vector(1 downto 0); in : in std_logic_vector(3 downto 0); out : out std_logic ); end multiplexer; architecture behavior of multiplexer is begin out <= in(conv_integer(sel)); end behavior; Textual description: HDL design 5 in 0 in 1 in 2 in 3 sel 0 sel 1 out

Conventional FPGA tool flow 6 SYNTHESIS MAP Input: Textual description of functionality Internal representation: LUT circuit Output: FPGA configuration PLACE HDL design Configuration ROUTE LUT circuit

Dynamic reconfiguration of FPGAs 7 Advantages: Smaller area Lower power usage Increased speed M1M1 M2M2 M3M3 Goal: area reduction with reduced reconfiguration time M1M1 M2M2 M3M3 Disadvantage: Reconfiguration time

Dynamic reconfiguration of FPGAs 8 M1M1 M2M2 M3M3 2 tool flows: Modular Dynamic Reconfiguration (MDR) Dynamic Circuit Specialization (DCS) M1M1 M2M2 M3M3

Modular Dynamic Reconfiguration (MDR) 9 Mode 1 SYNTHESIS MAP PLACE Configuration 1 ROUTE Mode 2 SYNTHESIS MAP PLACE Configuration 2 ROUTE

MDR Different modes are implemented independently Complete area is rewritten  Results in long reconfiguration times 10

Dynamic Circuit specialization Design with parameters: input signals that only change once a while Implement dependency on parameters using dynamic reconfiguration 11

Dynamic circuit specialization 12 Input: annotated textual description of functionality SYNTHESIS Param. HDL TMAP TPLACE Param. Conf. TROUTE Tunable circuit

entity multiplexer is port( --BEGIN PARAM sel : in std_logic_vector(1 downto 0); --END PARAM in : in std_logic_vector(3 downto 0); out : out std_logic ); end multiplexer; architecture behavior of multiplexer is begin out <= in(conv_integer(sel)); end behavior; Parameterised HDL design 13 in 0 in 1 in 2 in 3 sel 0 sel 1 out

Dynamic circuit specialization 14 SYNTHESIS Input: Annotated textual description of functionality Internal representation: Tunable Circuit Param. HDL TMAP TPLACE Param. Conf. TROUTE Tunable circuit

15 Tunable look-up table Tunable connection

Dynamic circuit specialization 16 Input: Annotated textual description of functionality Internal representation: Tunable Circuit Output: Parameterised configuration Param. HDL SYNTHESIS TMAP TPLACE Param. Conf. TROUTE Tunable Circuit 1A B0 0C1111 A = sel 0 AND sel 1 B = sel 1 C = sel 0 OR sel 1

Dynamic Circuit Specialization Reduced reconfiguration time Takes as input 1 parameterised design How to implement several modes with DCS? 17

Goal of our research Develop tool flow for dynamic reconfiguration of multi-mode circuits Reduce reconfiguration time Combined implementation of different modes:  Utilize similarities  Increase correlation between configurations of the different modes 18

Novel tool flow 19 Mode 1 SYNTHESIS MAP Mode 2 SYNTHESIS MAP Param. Conf. TROUTE Merge PLACE Configuration 1 ROUTE PLACE Configuration 2 ROUTE

Generating a Tunable multi-mode circuit 20

Combined placement: virtual 3D FPGA 21 Simultanous placement of different LUT circuits on FPGA Extension of a simulated annaeling placer

Different cost functions 22 CF RT : estimation of reconfiguration time (= number of switches that need to be rewritten in the routing) CF WL : estimation of total wire length Tunable circuit

Reconfiguration time optimization 23 Uses “edge matching” - previously proposed * Try to overlap connections of different modes Connections that overlap don’t require parameterised bits in the routing *M. Rullmann and R. Merker, “Maximum edge matching for reconfigurable computing,” Parallel and Distributed Processing Symposium, International, vol. 0, p. 179, 2006.

Wire-length optimization 24 Cost function that estimates total wire length needed by TRoute to implement Tunable circuit

Experiments 25 Implemented novel tool flow in our JAVA version of VPR Regular expression matching hardware, constant coefficient FIR filters, and general MCNC benchmarks Circuits of LBs Only 2 modes considered Comparison of MDR and DCS (this work) Metrics: Reconfiguration time Wire length (of each mode separately)

Wire length 26

Results 27

Results 28

Conclusions 27 Using combined placement and DCS: Around 5X speedup of reconfig. time Limited increase in wire length Better to optimize for wire length during combined placement: this also reduces reconfiguration time!

Future work 28 Combining logic circuits instead of LUT circuits Take configuration frames into consideration

Questions? An automatic tool flow for the combined implementation of multi-mode circuits