ECE-L304 Lecture 5

2 Step 3 Lab Complete 8-pin header Data Bus Test Port Resistor Array LED Array Timing & Filter Components Self-Clocked ADC DAC External Components

ECE-L304 Lecture 53 Step 4 Purpose Introduce the static RAM chip Write mode, read mode Introduce the address generator Step the address from 00H to FFH (256 steps) using 8 bits “H” indicates hexadecimal format Introduce control Record 256 words in RAM, then play back

ECE-L304 Lecture 54 This Week  Step 4 Prelab  Skim the data sheet for the 1 MB RAM chip  Look for control and timing information  Step 4 Lab Simulate a simple data acquisition system with memory Answer a few short questions

ECE-L304 Lecture 55 Static RAM An Introduction Static RAM is read/write storage that is volatile Volatile - when power is removed, contents are lost Words are written to or read from sites determined by the address location under RE/WE (read enable/write enable) control An 8k x 8 RAM has a 13-bit address bus giving 2 13 = bit locations, or 64kB (65,536) A 128k x 8 RAM has a 17-bit address bus, giving 2 17 = 131,072 8-bit locations, or 1MB

ECE-L304 Lecture 56 A[12-0] D[7-0] RE WE stable Static RAM Read and Write Timing Write Operation After the address and data have been stable for a setup time, pulse the write enable

ECE-L304 Lecture 57 Static RAM Read and Write Timing Read Operation Once the address is stable, raise the read enable After a settling time, the data is valid D[7-0] RE WE stable valid A[12-0]

ECE-L304 Lecture 58 What will you do? Part 1 Write two data bytes to two RAM locations and read them back Learn to display data in hex format in Probe Observe Read/Write operations and timing Part 2 Write 8-bit ADC data to 256 locations and read it back

ECE-L304 Lecture 59 Data Acquisition System Operation Repeat n times to store: Sample an analog signal Convert to digital Write to the next RAM location Repeat n times to retrieve: Read from next RAM location Convert to analog Display analog signal n = number of RAM locations

ECE-L304 Lecture 511 Address Generation RAM DAC ADC Control

ECE-L304 Lecture 512 Step 4 - Part 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 RE WE R7 R6 R5 R4 R3 R2 R1 R0 W7 W6 W5 W4 W3 W2 W1 W0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 RW0 RW1 DSTM1 A[16-0] DSTM2 RW[3-0] FORMAT=1111 0s us us us us us s us us us 0006 FORMAT=4444 RAM8kX8break R[7-0] W[7-0] FORMAT=44 0s 54 1us 36 2us XX DSTM3 R7 R6 R5 R4 R3 R2 R1 R0 W7 W6 W5 W4 W3 W2 W1 W0 S16 S4 S8

ECE-L304 Lecture 513 Step 4 - Part 1 Simulate the following activities Write data 54H from port W to address 5H Write data 36H from port W to address 6H Read the contents of address 5H to port R Read the contents of address 6H to port R

ECE-L304 Lecture 514 Step 4 - Part 2

ECE-L304 Lecture 515 Step 4 - Part 2 Why are the two AND gates (U8A, U12A) needed? The address must be set up and stable before the WRITE signal is applied

ECE-L304 Lecture 516 Step 4 - Part 2

ECE-L304 Lecture 517 Step 4 - Part 2

ECE-L304 Lecture 518 Step 4 - Part 2 Simulate the following activities Write 8-bit ADC data to the lowest 256 addresses in memory Read the lowest 256 addresses to the R port Generate an analog signal using these 8- bit words

ECE-L304 Lecture 519 The 8-Bit Counter The 74LS590 binary counter Used to generate addresses Ripple Carry Out pin makes it easy to set up multiple-chip counters

ECE-L304 Lecture 520 The 8-Bit Counter Multiple Chips G CCLK CCLKEN RCLK CCLR RCO A7 A6 A5 A4 A3 A2 A1 A0 LO HI CLK G CCLK CCLKEN RCLK CCLR RCO A7 A6 A5 A4 A3 A2 A1 A0 LO HI A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8

ECE-L304 Lecture 521 RAM Control RCO CLK

ECE-L304 Lecture 522 Your Hardware Static RAM NEC uPD431000A 128k x 8 Static RAM RAM - Random Access Memory 128k x 8 - storage for 131,072 8-bit words Data is transferred in and out in parallel 8-bit tristate data bus Input, output, high impedance Status controlled by CE1, CE2, WE, OE pins Control truth table on datasheet

ECE-L304 Lecture 523 Your Hardware Static RAM Address locations The 128k x 8 RAM has a 17-bit address bus (2 17 = 131,072) You will use the 16 address bits (2 16 = 65,536) generated by two 74LS590 chips and design a simple circuit to provide the 17th address bit This gives a total memory of 1024k You have the option of using 16 bits for less than full credit

ECE-L304 Lecture 524 Step 4 Deliverables Complete Part 1 Simulation Part 1 Schematic Part 1 Simulation Plot A[15-0], W[7-0], RW1, RW0, R[7-0] vs time over span of 0 to 4 us Are proper read/write timing rules followed? Relationships between address, data, RE, WE Is the data read from memory identical to what was written?

ECE-L304 Lecture 525 Step 4 Deliverables Complete Part 2 Simulation Part 2 Schematic Part 2 Simulation Plot W[7-0], R[7-0], WE, RE, RCO_, AIN, AOUT vs time over one complete read/write cycle Are proper read/write timing rules followed? Relationships between address, data, RE, WE Does the data read from memory and converted to analog (AOUT) match the input waveform (AIN) to the resolution of the system?

ECE-L304 Lecture 526 Step 4 Deliverables How would you correct the timing flaw at the transition from write to read? Repeat the simulation with the correction and include the results in your report. Why is there a lag time in the READ operation between the time RE goes high and when the data is valid?