CPE232 Introduction1 CPE 335 Computer Organization Introduction Dr. Gheith Abandah [Adapted from the slides of Professor Mary Irwin ( which in turn Adapted from Computer Organization and Design, Patterson & Hennessy, © 2005, UCB]

CPE232 Introduction2 Grading Information  Grading l Midterm Exam30% l Home works and Quizzes20% l Final Exam50%  Policies l Attendance is required l All submitted work must be yours l Cheating will not be tolerated l This course requires significant effort

CPE232 Introduction3 Course Content l Introduction l MIPS Instruction Set l Computer Arithmetic l CPU Performance Midterm Exam l Datapath Design l Control Design l Pipelining l Memory Hierarchy Final Exam

CPE232 Introduction4 Where is the Market? Millions of Computers

CPE232 Introduction5 By the architecture of a system, I mean the complete and detailed specification of the user interface. … As Blaauw has said, “Where architecture tells what happens, implementation tells how it is made to happen.” The Mythical Man-Month, Brooks, pg 45

CPE232 Introduction6 Instruction Set Architecture (ISA)  ISA: An abstract interface between the hardware and the lowest level software of a machine that encompasses all the information necessary to write a machine language program that will run correctly, including instructions, registers, memory access, I/O, and so on. “... the attributes of a [computing] system as seen by the programmer, i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls, the logic design, and the physical implementation.” – Amdahl, Blaauw, and Brooks, 1964 l Enables implementations of varying cost and performance to run identical software  ABI (application binary interface): The user portion of the instruction set plus the operating system interfaces used by application programmers. Defines a standard for binary portability across computers.

CPE232 Introduction7 ISA Type Sales PowerPoint “comic” bar chart with approximate values (see text for correct values) Millions of Processor

CPE232 Introduction8 Moore’s Law  In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 24 months (i.e., grow exponentially with time).  Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s. l 2300 transistors, 1 MHz clock (Intel 4004) l 16 Million transistors (Ultra Sparc III) l 42 Million transistors, 2 GHz clock (Intel Xeon) – 2001 l 55 Million transistors, 3 GHz, 130nm technology, 250mm 2 die (Intel Pentium 4) l 140 Million transistor (HP PA-8500)

CPE232 Introduction9 Processor Performance Increase SUN-4/260MIPS M/120 MIPS M2000 IBM RS6000 HP 9000/750 DEC AXP/500 IBM POWER 100 DEC Alpha 4/266 DEC Alpha 5/500 DEC Alpha 21264/600 DEC Alpha 5/300 DEC Alpha 21264A/667 Intel Xeon/2000 Intel Pentium 4/3000

CPE232 Introduction10 DRAM Capacity Growth 16K 64K 256K 1M 4M 16M 64M 128M 256M 512M

CPE232 Introduction11 Impacts of Advancing Technology  Processor l logic capacity:increases about 30% per year l performance:2x every 1.5 years  Memory l DRAM capacity:4x every 3 years, now 2x every 2 years l memory speed:1.5x every 10 years l cost per bit:decreases about 25% per year  Disk l capacity:increases about 60% per year ClockCycle = 1/ClockRate 500 MHz ClockRate = 2 nsec ClockCycle 1 GHz ClockRate = 1 nsec ClockCycle 4 GHz ClockRate = 250 psec ClockCycle

CPE232 Introduction12 Example Machine Organization  Workstation design target l 25% of cost on processor l 25% of cost on memory (minimum memory size) l Rest on I/O devices, power supplies, box CPU Computer Control Datapath MemoryDevices Input Output

CPE232 Introduction13 PC Motherboard Closeup

CPE232 Introduction14 Inside the Pentium 4 Processor Chip