Chalmers University of Technology FlexSoC Seminar Series – Page 1 Power Estimation FlexSoc Seminar Series – Daniel Eckerbert

Chalmers University of Technology FlexSoC Seminar Series – Page 2 Outline Why power estimation? Power macromodeling Future directions for power estimation Most pictures (non-Matlab-plots) are courtesy of Intel Corp.

Chalmers University of Technology FlexSoC Seminar Series – Page 3 Why Power Estimation? (Conference-Presentation Answer) Heat removal is expensive (fans, heat-sinks) Energy stored in battery is limited Power delivery is expensive (area, reliability, verification, packaging)

Chalmers University of Technology FlexSoC Seminar Series – Page 4 Why Power Estimation? (FlexSoC Answer) Compiler optimizations “Designing” range of chips for certain applications ??? You tell me!

Chalmers University of Technology FlexSoC Seminar Series – Page 5 Power Reduction Techniques Activity reduction Supply voltage scaling Leakage reduction (cut-off techniques, stacking etc) But, by how much does the power of a specific design needs to be reduced? And which power mechnism constitutes a problem?

Chalmers University of Technology FlexSoC Seminar Series – Page 6 Power Dissipation Basics

Chalmers University of Technology FlexSoC Seminar Series – Page 7 From Where Does the Power Increase Stem?

Chalmers University of Technology FlexSoC Seminar Series – Page 8 Increased Integration

Chalmers University of Technology FlexSoC Seminar Series – Page 9 Increased Integration 120 billion transistors per wafer!!! SRAM chips fabricated on a 300mm wafer

Chalmers University of Technology FlexSoC Seminar Series – Page 10 Increased Density

Chalmers University of Technology FlexSoC Seminar Series – Page 11 Power Density

Chalmers University of Technology FlexSoC Seminar Series – Page 12 Heat Removal (die)

Chalmers University of Technology FlexSoC Seminar Series – Page 13 Heat Removal (package)

Chalmers University of Technology FlexSoC Seminar Series – Page 14 Power Macro Modeling

Chalmers University of Technology FlexSoC Seminar Series – Page 15 Architecture Level Power Macromodeling à la Wattch P=0.1*P sw (α max )+P sw (α,state)

Chalmers University of Technology FlexSoC Seminar Series – Page 16 What Do We Want from a Power Estimation Methodology? Accurate Fast Provide information for power reduction

Chalmers University of Technology FlexSoC Seminar Series – Page 17 Levels of Power Estimation

Chalmers University of Technology FlexSoC Seminar Series – Page 18 Why Use Macro Models? Circuit simulations excessively time- and memory-consuming Designers need to run long traces to compare solutions (only possible using macro models)

Chalmers University of Technology FlexSoC Seminar Series – Page 19 Estimation Tool Run-Times Run-timeHSpice * PowerMill * Macro ** 16b Han- Carlson 12d14h8h49m (30x) 6m43s (2700x / 80x) 8b Multiplier29d6h17h37m (40x) 9m42s (4300x / 100x) 32b MultiplierN/A14d10h2h2m (N/A / 170x) * Highly optimized code by team of software designers ** Highly unoptimized C++ code by one overworked circuit designer

Chalmers University of Technology FlexSoC Seminar Series – Page 20 Precision Circuit simulations give full or close to full precision (depending on extraction) Macro modeling can give range of precision levels (with a maximum precision determined by methodology) Macro model precision is limited by the characterization

Chalmers University of Technology FlexSoC Seminar Series – Page 21 Power Estimation Flow Characterization –Requires lower level simulations –Has to support maximum precision –One-time only, can afford to be slow Estimation –Macro-model only –Can support multiple levels of precision –Frequently run, has to be fast

Chalmers University of Technology FlexSoC Seminar Series – Page 22 Characterization

Chalmers University of Technology FlexSoC Seminar Series – Page 23 Estimation

Chalmers University of Technology FlexSoC Seminar Series – Page 24 Switching Power (Circuit Level)

Chalmers University of Technology FlexSoC Seminar Series – Page 25 Switching Power (Early Power Macro Models)

Chalmers University of Technology FlexSoC Seminar Series – Page 26 Switching Power (VLSI Research Group Style) Equation-based 0→1 tracking, even for intermediate nodes depending on accuracy Physical model based on nodal capacitances and voltage swings Enables semi-automatic characterization

Chalmers University of Technology FlexSoC Seminar Series – Page 27 Short-Circuit Power (Circuit Level)

Chalmers University of Technology FlexSoC Seminar Series – Page 28 Short-Circuit Power (Macro Model)

Chalmers University of Technology FlexSoC Seminar Series – Page 29 Interconnect Modeling

Chalmers University of Technology FlexSoC Seminar Series – Page 30 CRC

Chalmers University of Technology FlexSoC Seminar Series – Page 31 RLC

Chalmers University of Technology FlexSoC Seminar Series – Page 32 Subthreshold-Leakage Power

Chalmers University of Technology FlexSoC Seminar Series – Page 33 Subthreshold-Leakage Power (Circuit Level)

Chalmers University of Technology FlexSoC Seminar Series – Page 34 Subthreshold-Leakage Power Stacking effects Long settling times …?

Chalmers University of Technology FlexSoC Seminar Series – Page 35 Subthreshold-Leakage Power (Macro Model) Equation-based model considering on- and off-states of the transistors constituting the gate Enables semi-automatic characterization Possible extensions for stacking Possible extensions for multiple clock-cycle settling times

Chalmers University of Technology FlexSoC Seminar Series – Page 36 Gate-Leakage Power

Chalmers University of Technology FlexSoC Seminar Series – Page 37 Oxide Thickness 12 Å

Chalmers University of Technology FlexSoC Seminar Series – Page 38 Oxide Thickness

Chalmers University of Technology FlexSoC Seminar Series – Page 39 Gate-Leakage Power (Circuit Level) Enough equations and theory to use up the entire FlexSoC seminar series

Chalmers University of Technology FlexSoC Seminar Series – Page 40 Gate-Leakage Power (Macro Model) Equation-based model considering on- and off-states of the transistors constituting the gate Enables semi-automatic characterization Complications include leakage paths originating in one gate and ending up in another gate

Chalmers University of Technology FlexSoC Seminar Series – Page 41 Separating Power Dissipation Mechanisms

Chalmers University of Technology FlexSoC Seminar Series – Page 42 Leakage Power Increase

Chalmers University of Technology FlexSoC Seminar Series – Page 43 Active vs. Leakage Power

Chalmers University of Technology FlexSoC Seminar Series – Page 44 Separation of Mechanisms (Rise- and Fall-Times)

Chalmers University of Technology FlexSoC Seminar Series – Page 45 Separation of Mechanisms (Supply-Voltage Scaling)

Chalmers University of Technology FlexSoC Seminar Series – Page 46 Mismatch for Methodologies without a Leakage Component

Chalmers University of Technology FlexSoC Seminar Series – Page 47 Mismatch for Methodologies without Leakage or Dynamica Frequency and Supply Scaling

Chalmers University of Technology FlexSoC Seminar Series – Page 48 Added Complications

Chalmers University of Technology FlexSoC Seminar Series – Page 49 Complex Gates Most circuit-level models are only valid for a single transistor or an inverter Macromodels have to be able to account for large components, 32b multipliers etc Complexity increases super-linearly with the number of transistors in the component

Chalmers University of Technology FlexSoC Seminar Series – Page 50 Non-Conforming Components There are classes of components which do not conform to the presented basic models: Clock generators Memories etc

Chalmers University of Technology FlexSoC Seminar Series – Page 51 Clock Generation (DLL)

Chalmers University of Technology FlexSoC Seminar Series – Page 52 Clock Generators (Delay Element)

Chalmers University of Technology FlexSoC Seminar Series – Page 53 Non-Linear Frequency Dependence for Certain Types of Components

Chalmers University of Technology FlexSoC Seminar Series – Page 54 Dynamic Precision Different architectures might impose different precision requirements for different components (static during estimation) Different operating modes might warrant different need for precision (changes during estimation)

Chalmers University of Technology FlexSoC Seminar Series – Page 55 Conclusions Power estimation is not simply about averaging the current through the supplies Circuit simulation is too slow A lot of research is needed to enable high- level power estimation for future designs: some in mechanism modeling but more importantly in the estimation framework

Chalmers University of Technology FlexSoC Seminar Series – Page 56 Power estimation is not as easy as it looks