EEE2243 Digital System Design Chapter 3: Elementary Components by Muhazam Mustapha, February 2012
Learning Outcome By the end of this chapter, students are expected to understand a few elementary components in digital system Decoder Multiplexer Demultiplexer T Flip-flop JK Flip-flop
Chapter Content Decoder Multiplexer Demultiplxer T Flip-flop JK Flip-flop
Decoder
Decoder A decoder is a combinational circuit that activates its output according to the binary value of its input General block diagram of active high 3-bit decoder: O0 3-to-8 Decoder O1 If I2I1I0 = 010, O2 will be set to HIGH, the rest will be LOW O2 I0 O3 I1 O4 I2 O5 O6 O7
Decoder Most of the decoders available in the market are inverted output (active low): O0 3-to-8 Decoder O1 If I2I1I0 = 010, O2 will be set to LOW, the rest will be HIGH O2 I0 O3 I1 O4 I2 O5 O6 O7
Decoder General truth table and circuit of 2-to-4 active high decoder: 1
Decoder General truth table and circuit of 2-to-4 active high decoder: 1
Decoder Verilog From the definition of decoder it might be obvious now that it easier to write its Verilog code in Boolean algebra rather than behavioral approach Active high decoder: module Decoder2to4(codein, codeout); input [1:0] codein; output [3:0] codeout; assign codeout[0] = ~codein[1] & ~codein[0]; assign codeout[1] = ~codein[1] & codein[0]; assign codeout[2] = codein[1] & ~codein[0]; assign codeout[3] = codein[1] & codein[0]; endmodule
Decoder Verilog Active low decoder: module Decoder2to4(codein, codeout); input [1:0] codein; output [3:0] codeout; assign codeout[0] = ~(~codein[1] & ~codein[0]); assign codeout[1] = ~(~codein[1] & codein[0]); assign codeout[2] = ~( codein[1] & ~codein[0]); assign codeout[3] = ~( codein[1] & codein[0]); endmodule
Multiplexer
Multiplexer A multiplexer (mux) is a combinational circuit that transfers its MULTI line inputs to a SINGLE line output according to the binary value of some selector lines General block diagram: I0 I1 I2 8-to-1 Mux I3 Output I4 If S2S1S0 = 010, value at I2 will be sent to Output I5 I6 I7 S2 S1 S0
Multiplexer General truth table of 8-to-1 multiplexer: S1 S0 Output I0 I0 1 I1 I2 I3
Multiplexer Based on the previous truth table, multiplexer can be built using decoder: S1 S0 Decoder I3 I2 Multiplexer Output I1 I0
Multiplexer The simplified circuit: S1 S0 I0 I1 Output I2 I3
Multiplexer Verilog Multiplexer is better be defined in behavioral approach module Mux4to1(sel, lin, lout); input [3:0] lin; input [1:0] sel; output lout; reg lout; always@(sel) begin case (sel) 0: lout = lin[0]; 1: lout = lin[1]; 2: lout = lin[2]; 3: lout = lin[3]; endcase end endmodule
Demultiplexer
Demultiplexer A demultiplexer (demux) is a combinational circuit that transfers its SINGLE line input to one of its MULTI line outputs according to the binary value of some selector lines General block diagram: Output O0 O1 1-to-8 Demux O2 O3 Input O4 If S2S1S0 = 010, value at Input goes O2 O5 O6 O7 S2 S1 S0
Demultiplexer Since a demux sends the input to only one output, the rest (non-active outputs) will be all HIGH (active low) or all LOW (active high) In this sense demux behaves like a decoder As a matter of fact we can build demux using decoder with gates at the outputs
Demultiplexer Active HIGH construct: Input O0 3-to-8 Decoder O1 O2 S0 The corresponding Verilog is left as exercise or tutorial or quiz
Demultiplexer Active LOW construct: Input O0 3-to-8 Decoder O1 O2 S0 The corresponding Verilog is left as exercise or tutorial or quiz
T & JK Flip-flops
T Flip-flop Toggles if T is high, otherwise stay Characteristic equation: T Q T Q Q* 1 clk Q
T Flip-flop Since in Verilog (any HDL) and FPGA design all flip-flops are D, we need to add some surrounding circuit if we want T flip-flops: T D Q clk Q The corresponding Verilog is left as exercise or tutorial or quiz
JK Flip-Flop Characteristic equation: J K Q Next Q (Q*) 1 Stay J Q clk 1 Stay J Q clk K Q Reset Characteristic equation: Set Toggle
JK Flip-flop Surrounding circuit for JK flip-flops: Q J clk Q The corresponding Verilog is left as exercise or tutorial or quiz