MOV,MOVM,COP,FLL,BSL,BSR, FRD,TOD

Slides:



Advertisements
Similar presentations
ECT 464 Lecture 22 Siemens Instructions 1. Today’s Quote: The best way to get the last word is to apologize. If you have been trapped by what you said,
Advertisements

Microprocessors.
INSTRUCTION SET ARCHITECTURES
There are two types of addressing schemes:
Copyright © 2005 Rockwell Automation, Inc. All rights reserved. 1 Micro Logix 1100 RSLogix 500 LAB#2 Timing, Counting & Comparing.
PLC Timer Instructions
Copyright © 2002 Delmar Thomson Learning Chapter 11 Processor Data Organization.
Copyright © 2002 Delmar Thomson Learning Chapter 12 Basic Relay Instructions.
The 8085 Microprocessor Architecture
SOFTWARE ARCHITECTURE OF THE 8088 AND 8086 MICROPROCESSORS
Microprocessor and Microcontroller
Switchgears Control Using SCADA System Based on PLC
Instruction Set Architecture & Design
TK 2633 Microprocessor & Interfacing Lecture 3: Introduction to 8085 Assembly Language Programming (2) 1 Prepared By: Associate Prof. Dr Masri Ayob.
Memory - Registers Instruction Sets
Room: E-3-31 Phone: Dr Masri Ayob TK 2633 Microprocessor & Interfacing Lecture 1: Introduction to 8085 Assembly Language.
Computer Architecture
Gursharan Singh Tatla Block Diagram of Intel 8086 Gursharan Singh Tatla 19-Apr-17.
Unit-1 PREPARED BY: PROF. HARISH I RATHOD COMPUTER ENGINEERING DEPARTMENT GUJARAT POWER ENGINEERING & RESEARCH INSTITUTE Advance Processor.
Chapter 19 Fundamental PLC Programming
Programmable Logic Controllers
Advanced Instructions Most PLCs now support more advanced functions such as Floating point math, Boolean operations, Shifting, Sequencing, Program control.
Programmable Logic Controllers
Introduction to PLC Operation
Copyright © 2002 Delmar Thomson Learning Chapter 17 Sequencer Instructions.
MicroLogix Packaged Controllers Programmable Controller Basics Memory & Data.
Machine Instruction Characteristics
Memory Layout and SLC500™ System Addresses. Processor Memory Division An SLC 500 processor's memory is divided into two storage areas. Like two drawers.
Memory Layout and SLC500™ System Addresses. Processor Memory Division An SLC 500 processor's memory is divided into two storage areas. Like two drawers.
Stack Stack Pointer A stack is a means of storing data that works on a ‘Last in first out’ (LIFO) basis. It reverses the order that data arrives and is.
Processor Data Organization
Memory Layout and SLC500 System Addresses. Processor Memory Division An SLC 500 processor's memory is divided into two storage areas. Like two drawers.
Storing and Organizing Data. Why Do I Need to Understand How Data Is Represented? In order to install, program,maintain, and troubleshoot today’s PLCs,
Counters. Counter Applications Counters count events such as the number of: Parts passing a certain point on a conveyor system Good parts/bad parts manufactured.
Programmable Logic Controllers
Interrupt driven I/O. MIPS RISC Exception Mechanism The processor operates in The processor operates in user mode user mode kernel mode kernel mode Access.
Chapter 10 Instruction Sets: Characteristics and Functions Felipe Navarro Luis Gomez Collin Brown.
Introduction to PLC Operation
Digital Computer Concept and Practice Copyright ©2012 by Jaejin Lee Control Unit.
1 The Instruction Set Architecture September 27 th, 2007 By: Corbin Johnson CS 146.
Interrupt driven I/O Computer Organization and Assembly Language: Module 12.
What is a program? A sequence of steps
Sequencers SQO,SQC,SQL.
MICROPROCESSOR DETAILS 1 Updated April 2011 ©Paul R. Godin prgodin gmail.com.
Instruction Sets. Instruction set It is a list of all instructions that a processor can execute. It is a list of all instructions that a processor can.
1 Basic Processor Architecture. 2 Building Blocks of Processor Systems CPU.
Introduction to Intel IA-32 and IA-64 Instruction Set Architectures.
Digital Computer Concept and Practice Copyright ©2012 by Jaejin Lee Control Unit.
Computer and Information Sciences College / Computer Science Department CS 206 D Computer Organization and Assembly Language.
Riyadh Philanthropic Society For Science Prince Sultan College For Woman Dept. of Computer & Information Sciences CS 251 Introduction to Computer Organization.
Programmable Logic Controller
Chapter 5.
Chapter 11 & 13 PLC Math Instructions Permission granted to reproduce for educational use only. 11 PLC Compare, Jump, and MCR Instructions.
Computer Architecture. Instruction Set “The collection of different instructions that the processor can execute it”. Usually represented by assembly codes,
1 Introduction to PLCs: Programming Counters ELMT Basic Programmable Logic Controllers Chapter 0x_W Source: www Based on Ch 8 of Frank D. Petruzella.
Chapter 5.
Assembly Language Programming of 8085
8086 Microprocessor.
Chapter 10 © 2011, The McGraw-Hill Companies, Inc.
..
An Introduction to Microprocessor Architecture using intel 8085 as a classic processor
Chapter 12 © 2011, The McGraw-Hill Companies, Inc.
Chapter 11 © 2011, The McGraw-Hill Companies, Inc.
Comparison and Data-handling Instructions
Comparison and Data-Handling Instructions
Programmable Controller Basics Files And Programs
Shift & Rotate Instructions)
ECEG-3202 Computer Architecture and Organization
ECEG-3202 Computer Architecture and Organization
Data manipulation Instructions
Presentation transcript:

MOV,MOVM,COP,FLL,BSL,BSR, FRD,TOD Word And File Moves MOV,MOVM,COP,FLL,BSL,BSR, FRD,TOD

Move (MOV) Description: The MOV instruction is an output instruction that copies the Source address to a Destination. As long as the rung remains true, the instruction moves the data each scan. The source and destination data types should be the same because the instruction does not perform a conversion.

Move (MOV): This out put instruction moves the source value to the destination location. As long as the rung remains true, the instruction moves the data each scan. Entering Parameters: Enter the following parameters when programming this instruction: Source is the address or constant of the data you want to move. Destination is the address where the instruction moves the data. Application Note: If you wish to move one word of data without affecting the math flags, use a copy (COP) instruction with a length of 1 word instead of the MOV instruction.

Entering Parameters: To program this instruction, you must provide the processor with the following:

Masked Move (MVM) Description: The MVM instruction is an output instruction that copies the Source to a Destination, and allows portions of the data to be masked. As long as the rung remains true, the instructions moves data each scan. You can use the MVM instruction to copy I/O image, binary, or integer values.

Masked Move (MVM): The MVM instruction is a word instruction that moves data from a source location to a destination, and allows portions of the destination data to be masked by a separate word. As long as the rung remains true, the instruction moves the data each scan. Entering Parameters: Enter the following parameters when programming this instruction: Source is the address of the data you want to move. Mask is the address of the mask through which the instruction moves data; the mask can be a hex value (constant). Destination is the address where the instruction moves the data.

Entering Parameters: To program this instruction, you must provide the processor with the following:

Use the shift register instruction to stimulate the movement or flow of parts and information.

Copy File (COP) The destination file type determines the number of words that an instruction transfers. After a COP or FLL instruction is executed, index register S: 24 is cleared to zero. This instruction copies blocks of data from one location into another. It uses no status bits. If you need an enable bit, program an output instruction (OTE) in parallel using an internal bit as the output address.

Entering Parameters: Enter the following parameters when programming this instruction: Source is the address of the file you want to copy. You must use the file indicator (#) in the address. When using either an SLC 5/03 (OS301 or higher), SLC 5/04 (OS401), or SLC 5/05 processor, floating point and string values are supported. Destination is the starting address where the instruction stores the copy. You must use the file indicator (#) in the address. When using either and SLC 5/03 (OS301 or higher), SLC 5/04 (OS401), or SLC 5/05 processor, floating point and string values are supported. Length is the number of elements in the file you want to copy. * for SLC processors, if the destination file is 3 words per element (timer or counter), you can specify a maximum length of 42. If the destination file type is 1 word per element , you can specify a maximum length of 128 words.

NOTE: The maximum lengths apply when the source is of the same file type. All elements are copied from the source file into the destination file each time the instruction is executed. Elements are copied in ascending order. If your destination file type is a timer, counter, or control file, be sure that the source words corresponding to the status words of your destination file contains zeros. Be sure that you accurately specify the starting address and length of the data block you are copying. The instruction will not write over a file boundary (such as between files N16 and N17) at the destination. An error occurs if a write is attempted over a file boundary. You can perform file shifts by specifying a source element address one or more elements greater than the destination element address within the same file. This shifts data to lower element addresses.

Fill File (FLL) This instruction loads elements of a file with either a program constant or value from an element address. The instruction fills the words of a file with a source value. It uses no status bits. If you need an enable bit, program a parallel output that uses a storage address.

Entering Parameters: Enter the following parameters when programming this instruction. Source is the program constant or element address. The file indicator (#) is not required for an element address. When using either an SLC5/03 (OS301 or higher), SLC 5/04 (OS401), or SLC5/05 processor, floating point and string values are supported. Destination is the destination starting address of the file you want to fill. You must use the file indicator (#) in the address. When using either an SLC5/03 (OS301 or higher), SLC 5/04 (OS401), or SLC5/05 processor, floating point and string values are supported. Length is the number of elements in the file you want filled. - for SLC processors, if the destination file type is 3 words per element (timer or counter), you can specify a maximum length of 42. If the destination file type is 1 word per element, you can specify a maximum length of 128 words. All elements are filled from the source value (typically a constant) into the specified destination file each scan the rung is true. Elements are filled in ascending order. The instruction will not write over a file boundary (such as between filesN16 and N17) at the destination. An error is declared if a write is attempted over a file boundary.

Control Data File (R6:) These instructions use various control bits. These are 3-word elements, used with Bit Shift, FIFO, LIFO, Sequencer instructions, and ASCII instructions ABL, ACB, AHL, ARD, ARL, AWA, and AWT. Word 0 is the status word, word 1 indicates the length of stored data, and word 2 indicates position. This is shown in the following figure:

EN EU DN EM ER UL IN FD error code In the control element there are eight status bits and an error code byte. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 word EN EU DN EM ER UL IN FD error code Length of Bit array or file (LEN) Bit Pointer or Position (POS) 1 2

Addressable Bits: Addressable Words: EN= enable LEN= length EU= unload enable POS= position DN= done EM= stack empty ER= error (error code value is displayed in HEX and is not addressable) UL= unload (bit shift only) IN= inhibit (this is the running bit (RN bit 9) for ASCII instructions) FD= found (SQC only)

Using Bit Shift Instructions: Description: Bit shift instructions shift all bits within the specified address one bit position with each false-to-true rung transition. These instructions are: * Bit Shift Left (BSL) * Bit Shift Right (BSR)

Bit Shift Left (BSL) & Bit Shift Right (BSR): BSL and BSR are output instructions that load data into a bit array one bit at a time. The data is shifted through the array, then unloaded one bit at a time. Using BSL: When the rung goes from false-to-true, the processor sets the enable bit (EN bit 15) and the data block is shifted to the left (to a higher bit number) one bit position. The specified bit at the bit address is shifted into the first bit position. The last bit is shifted out of the array and stored in the unload bit (UL bit 10). The shift is completed immediately. For wraparound operation, set the position of the bit address to the last bit of the array or to the UL bit, whichever applies. The figure below illustrates how the Bit Shift Left instruction works. If you wish to shift more than one bit per scan, you must create a loop in your application using the JMP, LBL, and CTU instructions.

Using BSR: When the rung goes from false-to-true, the enable bit (EN bit 15) is set and the data block is shifted to the right (to a lower bit number) one bit position. The specified bit at the bit address is shifted into the last bit position. The first bit is shifted out of the array and stored in the unload bit (UL bit 10) in the status byte of the control element. The shift is completed immediately. For wraparound operation, set the position of the bit address to the first bit of the array or the UL bit, whichever applies.

Entering Parameters: To program a bit shift instruction, you need to provide the processor with the following information:

Using Status Bits: To use the BSL and BSR instruction correctly, examine status bits in the control element. You address these bits by mnemonic.

Important: When enabled, the bit pointer is set to the value of the length the bit array is shifted. After all of the bits are shifted, the instruction resets the .EN, .ER, and .DN bits are the bit pointer when input conditions go false.

The conversion instructions convert integer to BCD to integer (using TOD and FRD). Use TOD and FRD for signals to/from BCD I/O devices, for display purposes, or for number compatibility with PLC-2 family processors.

Convert to BCD (TOD) Use this instruction to convert 16-bit integers into BCD values. With Fixed and SLC 5/01 processors, the destination can only be the math register. With SLC 5/02 and higher processors and MicroLogix 1000 ocntrollers, the destination parameter can be word address in any data file, or it can be the math register, S;13 and S:14. If the integer value you enter is negative the absolute value of the number is used for conversion.

Convert from BCD (FRD): Use this instruction to convert BCD values to integer values. With Fixed and SLC 5/01 processors, the source can only be the math register. With SLC 5/02 and higher processors and Mirologix 1000 controllers, the source parameter can be a word address in any data file, or it can be the math register, S:13.

Convert to BCD (TOD) Description: Use the TOD instruction to convert an integer value to a BCD value. If the integer value is greater than 9999, the processor stores 9999 and sets the overflow bit. If the integer value is negative, the processor stores 0 in the destination ands sets the overflow and zero status bits.

Convert from BCD (FRD)

Description: Use the FRD instruction to convert a BCD value to an integer value. Convert BCD values to integer before you manipulate those values with ladder logic because the processor treats BCD values as integer values. The actual BCD value may be lost or distorted.