Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics Engineering National Taiwan University October 24,

2 Outline ․ Contributions ․ Introduction ․ Problem Formulation ․ The Routing Algorithm ․ Conclusions

3 Outline ․ Contributions ․ Introduction ․ Problem Formulation ․ The Routing Algorithm ․ Conclusions

4 Contributions ․ Present the first Area-I/O RDL routing algorithm for chip-package co-design in the literature  Propose a network-flow based routing algorithm  Consider multi-RDL assignment  Extra consider the assignment among block ports and I/O pads ․ Try to achieve 100% RDL routability and the optimal global-routing wirelength

5 Outline ․ Contributions ․ Introduction ․ Problem Formulation ․ The Routing Algorithm ․ Conclusions

6 Flip-Chip Technology ․ Provides a high chip-density solution to the demand for more I/O pads of VLSI designs ․ Is popular for high-speed and low-power applications  Lower power consumption  Smaller delay  Smaller inductance effect Flip-Chip Package Bump ball I/O pad (I/O buffer)Bump padFlip-Chip (Die)

7 Flip-Chip Routing ․ In modern flip-chip designs, place the I/O pads into the whole area of the die ․ Use extra metal layers, called Re-Distribution Layers (RDL’s), to redistribute the I/O pads to the bump pads ․ Apply an RDL router to route the I/O pads to the bump pads Cross section of RDL RDL routing example Bump pad I/O pad

8 Chip-Package Co-Design ․ Extra consider the assignment among block ports and I/O pads  Allow an RDL router to choose a proper I/O buffer for each net ․ Have more flexibility to place blocks and I/O buffers  Reduce the constraints from the connections between block ports and I/O buffers to have better floorplanning results and shorter CUP times PackageChip Bump pad Block Block port I/O buffer I/O pad 2

9 Flip-Chip Routing Structure ․ Interval: two adjacent bump pads ․ Tile: four adjacent bump pads ․ l i /w j : column i/row j of bump pads Package-level structureChip-level structure

10 Outline ․ Contributions ․ Introduction ․ Problem Formulation ․ The Routing Algorithm ․ Conclusions

11 Problem Definition ․ Problem: Multi-layer pin assignment and Area-I/O RDL routing for chip-package co-design ․ Inputs:  A die with block ports and I/O pads (buffers in different sizes)  A flip-chip package with bump pads  The number of RDL’s  Design rules ․ Output: A routing solution without design-rule violation ․ Objective: Connect all nets to minimize the total wirelength

12 Outline ․ Contributions ․ Introduction ․ Problem Formulation ․ The Routing Algorithm ․ Conclusions

13 The Routing Flow Blocks (Block Ports), I/O Buffers (I/O Pads), Bump Pads, # RDL’s Global RoutingRDL Routing RDL Routing Result Output Chip-level I/O Netlist Output Chip-level Routing 1. Construct a flow network to simultaneously assign and route block ports to bump pads via I/O pads 2. Consider routing resource in the flow network to avoid overflow 1. Find a routable net order 2. Refine the global-routing paths to meet design rules

14 The Routing Flow Blocks (Block Ports), I/O Buffers (I/O Pads), Bump Pads, # RDL’s Global RoutingRDL Routing RDL Routing Result Output Chip-level I/O Netlist Output Chip-level Routing 1. Construct a flow network to simultaneously assign and route block ports to bump pads via I/O pads 2. Consider routing resource in the flow network to avoid overflow 1. Find a routable net order 2. Refine the global-routing paths to meet design rules

15 Intermediate and Tile Nodes Insertion ․ Tile node: at the middle of each tile ․ Interval node: at the middle of each interval Bump pad Intermediate node Tile node I/O pad

16 Basic Network Formulation ․ Min-Cost Max-Flow (MCMF) Algorithm (Concurrent Assignment)  Nodes: block port p ∈ P, I/O pad q ∈ Q, bump pad b ∈ B, intermediate node d ∈ D, tile node t ∈ T  Edges: e(p, q), e(q, b), e(q, t), e(q, d), e(d, b), e(d, t), e(t, b), and e(t, d)  Avoid crossing of edges => Avoid crossing of wires  Add intermediate nodes and tile nodes to avoid wire congestion I/O Pads (Type 1) d Tile p I/O Pads (Type 2) I/O Pads (Type 3) I/O Pads (Type 4) t b Block Port Cross section d t b Vertical view Intermediate node Bump pad

17 Cost/Capacity Assignment ․ Basic edge cost=edge length ․ There are 2/10 types of nodes/edges and their capacities are  C d /C t : maximum number of nets allowed to pass an interval/tile  Intermediate node=C d ; Tile node=C t  e(source, p)=1, e(p, q)=1, e(q, b)=1, e(q, d)=1, e(q, t)=1, e(d, b)=1, e(d, t)=C t, e(t, b)=1, e(t, d)=C d, and e(b, sink)=1 d t b b s t CdCd CtCt Tile node Intermediate node 1 Block port I/O pad Bump pad p p q q

18 Routing Completion Guarantee ․ Theorem:  Given a set of block ports, a set of I/O pads, and a set of bump pads, if there exists a feasible solution computed by the MCMF algorithm, we can guarantee 100% RDL routing completion Package-levelChip-level Bump pad Block Block port I/O buffer I/O pad 2

19 The Routing Flow Blocks (Block Ports), I/O Buffers (I/O Pads), Bump Pads, # RDL’s Global RoutingRDL Routing RDL Routing Result Output Chip-level I/O Netlist Output Chip-level Routing 1. Construct a flow network to simultaneously assign and route block ports to bump pads via I/O pads 2. Consider routing resource in the flow network to avoid overflow 1. Find a routable net order 2. Refine the global-routing paths to meet design rules

20 Passing-Point Assignment ․ After network solving, split edges to get independent nets without any wire crossing  According to the flows passing each tile node, refine edges  Split each intermediate node and edge to get final global- routing paths : Bump Pads : I/O Pads : Intermediate Nodes : Passing Points : Edges : Net Segments Tile Node Flow

21 : Bump Pad ․ Modify the net ordering determination (Hsu, in DAC-83) ․ Consist of 3 steps  Step 1: redraw the boundary  Step 2: decide the source s and destination d for each wire  Step 3: decide the net ordering by a stack ․ Apply maze routing : I/O Pad Net Ordering Determination and Maze Routing d 4 2’ 1 3 5’ 2 1’4’ 5 3’ s d s d ss d 1’ 5 2’ 3’ 1’2’3’5 : Passing Point : Net Segment 5 4 2’ 1 3 5’ 2 1’4’ 5 3’

22 Outline ․ Introduction ․ Problem Formulation ․ The Routing Algorithm ․ Conclusions

23 Conclusions ․ Propose a flip-chip router for chip-package co-design considering I/O assignment and total wirelength minimization ․ Try to achieve 100% RDL routability and the optimal global-routing wirelength by using network flow

24 Schedule ․ Stage 1 (1/2008 – 4/2008): done  Literature survey  Development of a placement and routing algorithm considering the objectives ․ Stage 2 (5/2008 – 7/2008): done  Implementation of the placement and routing algorithm ․ Stage 3 (8/2008 – 9/2008): done  Optimization of the objectives ․ Stage 4-1 (9/2008 – 11/2008): done  GUI generation and integration of all functions  Paper writing and documentation ․ (Extra) Stage 4-2 (9/2008 – )  Extensions to Etron designs ․ (Extra) Stage 4-3 (9/2008 – )  Study the Area-I/O Flip-Chip Routing for Chip-Package Co- Design