Operational-Amplifier Circuits C H A P T E R 12 Operational-Amplifier Circuits Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.1 The basic two-stage CMOS op-amp configuration. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12. 2 Small-signal equivalent circuit for the op amp in Fig. 12 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.4 Typical frequency response of the two-stage op amp. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12. 5 Small-signal equivalent circuit of the op amp in Fig. 12 Figure 12.5 Small-signal equivalent circuit of the op amp in Fig. 12.1 with a resistance R included in series with CC. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12. 6 A unity-gain follower with a large step input Figure 12.6 A unity-gain follower with a large step input. Since the output voltage cannot change immediately, a large differential voltage appears between the op-amp input terminals. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12. 7 Model of the two-stage CMOS op-amp of Fig. 12 Figure 12.7 Model of the two-stage CMOS op-amp of Fig. 12.1 when a large differential voltage is applied. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.8 Structure of the folded-cascode CMOS op amp. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.9 A more complete circuit for the folded-cascode CMOS amplifier of Fig. 12.8. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.10 Small-signal equivalent circuit of the folded-cascode CMOS amplifier. Note that this circuit is in effect an operational transconductance amplifier (OTA). Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.11 A folded-cascode op amp that employs two parallel complementary input stages to achieve rail-to-rail input common-mode operation. Note that the two “+” terminals are connected together and the two “–” terminals are connected together. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.12 (a) Cascode current mirror with the voltages at all nodes indicated. Note that the minimum voltage allowed at the output is Vt + 2VOV . (b) A modification of the cascode mirror that results in the reduction of the minimum output voltage to VOV. This is the wide-swing current mirror. The circuit requires a bias voltage VBIAS. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure E12.9 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.13 The 741 op-amp circuit: Q11, Q12, and R5 generate a reference bias current; IREF. Q10, Q9, and Q8 bias the input stage, which is composed of Q1 to Q7. The second gain stage is composed of Q16 and Q17 with Q13B acting as active load. The class AB output stage is formed by Q14 and Q20 with biasing devices Q13A, Q18, and Q19, and an input buffer Q23. Transistors Q15, Q21, Q24, and Q22 serve to protect the amplifier against output short circuits and are normally cut off. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure E12.11 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.14 The Widlar current source that biases the input stage. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.15 The dc analysis of the 741 input stage. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.16 The dc analysis of the 741 input stage, continued. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.17 The 741 output stage without the short-circuit protection devices. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.18 Small-signal analysis of the 741 input stage. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.19 The load circuit of the input stage fed by the two complementary current signals generated by Q1 through Q4 in Fig. 12.18. Circled numbers indicate the order of the analysis steps. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.20 Simplified circuits for finding the two components of the output resistance Ro1 of the first stage. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.21 Small-signal equivalent circuit for the input stage of the 741 op amp. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.22 Input stage with both inputs grounded and a mismatch ΔR between R1 and R2. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.23 Example 12.4: Analysis of the common-mode gain of the 741 input stage. Note that Ro = Ro9 || Ro10 , has been “pulled out” and shown separately, leaving behind ideal current sources Q9 and Q10. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.24 The 741 second stage prepared for small-signal analysis. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.25 Small-signal equivalent-circuit model of the second stage. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.26 Definition of Ro17. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.27 Thévenin form of the small-signal model of the second stage. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.28 The 741 output stage without the short-circuit-protection circuitry. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.29 Model for the 741 output stage. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.30 Circuit for finding the output resistance Rout. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure E12.23 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure E12.24 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.31 Cascading the small-signal equivalent circuits of the individual stages for the evaluation of the overall voltage gain. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.32 Bode plot for the 741 gain, neglecting nondominant poles. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.33 A simple model for the 741 based on modeling the second stage as an integrator. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12. 34 A unity-gain follower with a large step input Figure 12.34 A unity-gain follower with a large step input. Since the output voltage cannot change instantaneously, a large differential voltage appears between the op-amp input terminals. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.35 Model for the 741 op amp when a large positive differential signal is applied. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12. 36 Power supply requirements have changed considerably Figure 12.36 Power supply requirements have changed considerably. Modern BJT op amps are required to operate from a single supply VCC of 2 to 3 V. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.38 A self-biased current-reference source utilizing a Widler circuit to generate I = VT /R2ln(IS2/IS1) The bias voltages VBIAS1 and VBIAS2 are utilized in other parts of the op-amp circuit for biasing other transistors. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.39 The bias lines VBIAS1 and VBIAS2 provided by the circuit in Fig. 12.38 are utilized to bias other transistors and generate constant current I5 to I10. Both the transistor area and the emitter degeneration resistance value have to be appropriately scaled. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.40 For the input common-mode range to include ground voltage, the classical current-mirror-loaded input stage in (a) has to be replaced with the resistively-loaded configuration in (b) with the dc voltage drop across RC limited to 0.2–0.3 V. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12. 41 The complement of the circuit in Fig. 12. 40(b) Figure 12.41 The complement of the circuit in Fig. 12.40(b). While the input common-mode range of the circuit in Figure 12.40(b) extends below ground, here it extends above VCC. Connecting the two circuits in parallel, as will be shown, results in a rail-to-rail VICM range. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.42 Input stage with rail-to-rail input common-mode range and a folded-cascode stage to increase the gain. Note that all the bias voltages including VBIAS3 and VB are generated elsewhere on the chip. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.45 An op amp second stage incorporating the common-mode feedback circuit for the input stage. Note that the circuit generates the voltage VB needed to bias the cascode circuit in the first stage. Diode D is a Schottky-barrier diode which exhibits a forward voltage drop of about 0.4V. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.47 The output stage which is operated as class AB needs emitter follower buffers/drives to reduce the loading on the preceding stage and to provide the current gain necessary to drive QP and QN. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure 12.48 A more complete version of the output stage showing the circuits that establish the quiescent current in QP and QN. As well, this circuit forces a minimum current of (IQ / 2) to follow in the inactive output transistor, thus preventing the transistor from turning off and minimizing crossover distortion. Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure P12.16 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure P12.27 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure P12.39 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure P12.44 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.

Figure P12.63 Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc.