 Purpose of our project  Get real world experience in ASIC digital design  Use same tools as industry engineers  Get practical experience in microprocessor arch.  Learn how to interface hardware and software designed by our group and outside sources  Learn good design practices

 The team will build from scratch three peripherals for an open source processor core using RTL  The three peripherals will be:  UART  SMBUS version 1.0 – verified with 3rd party hardware/software  LCD Interface - Allows uP to interface to LCD screen on Altera DE2 Device Requirements  Implement method of using RAM and ROM for microprocessor  Have general input/output ports for controlling external devices  Device will run compiled C code from a compiler designed for reference controller  RTL will run on commercially available FPGA demo board  Design test applications to demonstrate device operability  Demonstrate stable behavior by executing a program the same way as the reference controller would  Learn the layout and extraction tools well enough to perform at least a partial layout  Develop a real world application for device

Final Deliverables:  Source RTL for all core, peripheral and system components  Test programs/simulations demonstrating system operability  Documentation on how to use device  Deliver one functional hardware unit Objectives:  During this project the team will work on developing the following skills  Developing working RTL code  Knowledge of revision control  Knowledge of FPGA design and use  Understanding of digital communication buses  Project management skills  Design for test principles

Research Peripheral Write in Verilog Simulate with Incisive Synthesize with Quartus for FPGA Test Software Requirements Write Software Test Design circuit in Multisim Transfer to Ultiboard Send out files to be milled Solder in partsTest

 SmartSVN Revision Control  Lets us save all our code revisions  Incisive  Used to simulate Verilog code  Quartus II  Used for analysis and synthesis  Multiboard  For circuit simulation  Ultiboard  For board layout  MSPGCC  Compiling software for demo processor  CodeBlocks  For developing PC software to interface with demo

SMBUSUART LCD Interface Demo PCB PC Serial Port LCD Screen Altera DE2 FPGA Eval Board MSP430 Core (Opencores.org) MSP430 Peripheral Interface Our Verilog

 Synthesizable 16 bit MCU written in Verilog  Heart of our project  Building a whole core would be very time consuming – Use open source code  Several choices – picked OpenMSP430 because of documentation, flexibility  Can use open source compiler to build code

An asynchronous way of sending a byte of data Data is communicated between two UARTs Only two wires needed for send/receive Our UART is full-duplex – can send and receive simultaneously A UART is used to interface low speed peripheral devices(ex. Keyboard, mouse)

Transmission scheme

Parts of a UART Baud generator Receiver Transmitter Control block

 Function:  In software an LCD command forces a long wait on the MSP430 because of the setup time for the LCD, preventing the MSP430 from doing useful work.  The LCD Interface will store these instructions and initialize the LCD and execute the instructions after the LCD setup time has pasted.  This will free up the MSP430 to do whatever it wants to.  This can all be done in software, but our solution greatly decreases code complexity

 How it was made:  First, we got the LCD to work with software to make sure we were sending to right signals  Second, we split up the Verilog into a initialization block and a control block.  Next, we used Quartus to dump the code on to the FPGA  Last, we wrote some software to write to our LCD through our UART and through the LCD Interface.

 Standard 2-way serial interface based on I 2 C  Created by Intel in 1995  Has bitrate of 10kHz to 100kHz  Used on many components for basic communication  Sensors, regulators, power management, D/A  Over 3000 components listed on DigiKey  Transfers are initiated by master device, slave responds according to commands

Graphic taken from

To MSP430To PCB Bus Interface Controller SCLK Gen

Requirements  Handle communication with computer using our designed UART  Display user configurable information on the DE2 board using our designed LCD controller  Communicate with the SMBUS peripherals on our demo board (temperature sensor, LED controller, EEPROM) using our designed SMBUS controller

 A way of demonstrating the functionality of our UART  Allows us to communicate with the OpenMSP430 running on the DE2  Command line program, written in C, sends and receives data through the serial port

CommandOutput lcd_clearClears the lcd screen lcd_write [message]Writes [message] to the DE2 lcd screen beginning from first line, first spot lcd_offTurns the lcd screen off lcd_tempDisplays temperature information on lcd screen tempDisplays current temperature on PC plottempDisplays a plot of the temperature over the last minute on PC using Octave (data read from EEPROM) string[n]Displays custom message [n] on PC

 We want to make sure things work before we start putting them together  Each new module of Verilog has its own folder with test files  Can quickly trace down problems using simulator  Found out that simulator does things differently than Quartus  Spent a lot of time fixing differences

Planned Budget

Semester # 2 DE2 Board Supplied by ECE department Semester #1 MSP430 Development kit $20 DE1 Board Supplied by Packet Digital

 Weather data gathering station: temperature, humidity, wind, etc  Portable measuring devices with LCD screen and PC interface  Processor cooling (using SMBUS temperature sensor and SMBUS fan controller)

UART  Larger buffer (e.g. 8 bytes)  Parity bit, stop bit, word size, and baud rate configuration registers LCD controller  Configurable LCD size SMBUS  Multibyte reads and writes  Fix output signals register

Victory is Ours  Completed objectives  All peripherals functioning correctly  Demo working correctly on DE2  Learned about digital design flow  Project management and organization  It has been a very positive learning experience

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