Lecture 4 section 2.4-?? As opposed to CISC – Complicated Instruction Set Architecture (ala the x86)

MIPS Reference Data

Class Participation 1. The following is a MIPS ML instruction: 00000010001100100100000000100000 What AL does it represent? (Use the green sheet to decode it). add $t0, $s1, $s2 As opposed to CISC – Complicated Instruction Set Architecture (ala the x86) b. The following is a MIPS AL instruction: add $t0, $s1, $s2 What is the ML MIPS equivalent? 00000010001100100100000000100000

Machine Language - Arithmetic Instruction Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18 Instruction Format: Do you know what the field names stand for? op rs rt rd shamt funct 000000 10001 10010 01000 00000 100000 For class handout

Machine Language - Arithmetic Instruction Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18 Instruction Format: Do you know what the field names stand for? op rs rt rd shamt funct 000000 10001 10010 01000 00000 100000 For lecture

MIPS Instruction Fields op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits op rs rt rd shamt funct for class handout

MIPS Instruction Fields op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits op rs rt rd shamt funct opcode indicating operation to be performed address of the first register source operand address of the second register source operand the register destination address for lecture shift amount (for shift instructions) function code that selects the specific variant of the operation specified in the opcode field

Machine Language - Load Instruction Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions previous format was R-type for register Example: lw $t0, 24($s2) Where's the compromise? op rs rt 16 bit number For class handout 35 18 8 24 100011 10010 01000 0000000000011000

Machine Language - Load Instruction Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions previous format was R-type for register Example: lw $t0, 24($s2) Where's the compromise? op rs rt 16 bit number For lecture destination address no longer in the rd field - now in the rt field offset limited to 16 bits - so can’t get to every location in memory (with a fixed base address) 35 18 8 24 100011 10010 01000 0000000000011000

Memory Address Location Example: lw $t0, 24($s2) Memory 0xf f f f f f f f 2410 + $s2 = 0x00000002 0x12004094 $s2 For class handout 0x0000000c Note that the offset can be positive or negative 0x00000008 0x00000004 0x00000000 data word address (hex)

Memory Address Location Example: lw $t0, 24($s2) Memory 0xf f f f f f f f 2410 + $s2 = 0x00000002 . . . 1001 0100 + . . . 0001 1000 . . . 1010 1100 = 0x120040ac 0x12004094 $s2 For lecture What is the address of the memory location that gets loaded into $t0? …10010100 …00011000 -------------- …10101100= 0x020040ac 0x0000000c Note that the offset can be positive or negative 0x00000008 0x00000004 0x00000000 data word address (hex)

Machine Language - Store Instruction Example: sw $t0, 24($s2) A 16-bit address means access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register $s2 op rs rt 16 bit number 43 18 8 24 101011 10010 01000 0000000000011000 For class handout

Machine Language - Store Instruction Example: sw $t0, 24($s2) A 16-bit address means access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register $s2 op rs rt 16 bit number 43 18 8 24 101011 10010 01000 0000000000011000 For lecture why is it 2**13 (2**15) and NOT 2**14 (2**16) like we just saw with memory (here we have to represent signed numbers so the most significant bit is the sign bit)

Assembling Code Remember the assembler code we compiled last lecture for the C statement A[8] = A[2] - b lw $t0, 8($s3) #load A[2] into $t0 sub $t0, $t0, $s2 #subtract b from A[2] sw $t0, 32($s3) #store result in A[8] Assemble the MIPS object code for these three instructions For class handout

Assembling Code Remember the assembler code we compiled for the C statement A[8] = A[2] - b lw $t0, 8($s3) #load A[2] into $t0 sub $t0, $t0, $s2 #subtract b from A[2] sw $t0, 32($s3) #store result in A[8] Assemble the MIPS code for these three instructions 35 lw 19 8 For lecture lw 35 19 8 8 sub 0 8 18 8 0 34 sw 43 19 8 32 sub 8 18 34 43 sw 19 8 32

Review: MIPS Data Types Bit: 0, 1 Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word Character: ASCII 7 bit code Decimal: digits 0-9 encoded as 0000b thru 1001b two decimal digits packed per 8 bit byte Integers: 2's complement Floating Point

Beyond Numbers Most computers use 8-bit bytes to represent characters with the American Std Code for Info Interchange (ASCII) So, we need instructions to move bytes around ASCII Char Null 32 space 48 64 @ 96 ` 112 p 1 33 ! 49 65 A 97 a 113 q 2 34 “ 50 66 B 98 b 114 r 3 35 # 51 67 C 99 c 115 s 4 EOT 36 $ 52 68 D 100 d 116 t 5 37 % 53 69 E 101 e 117 u 6 ACK 38 & 54 70 F 102 f 118 v 7 39 ‘ 55 71 G 103 g 119 w 8 bksp 40 ( 56 72 H 104 h 120 x 9 tab 41 ) 57 73 I 105 i 121 y 10 LF 42 * 58 : 74 J 106 j 122 z 11 43 + 59 ; 75 K 107 k 123 { 12 FF 44 , 60 < 76 L 108 l 124 | 15 47 / 63 ? 79 O 111 o 127 DEL see Figure 3.15 in the book for the complete listing - note that we are only using 7 of the 8 bits (7 bits gives us 127 encodings) - the extra bit can be used as a parity bit to detect single bit errors during transmission Note that upper and lower case letters differ by exactly 32 13 is carriage return 0 is Null (marking the end of string in C)

Loading and Storing Bytes MIPS provides special instructions to move bytes lb $t0, 1($s3) #load byte from memory sb $t0, 6($s3) #store byte to memory What 8 bits get loaded and stored? load byte places the byte from memory in the rightmost 8 bits of the destination register what happens to the other bits in the register? store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory I op rs rt 16 bit number load byte takes the contents of the byte at the memory address specified, zero-extends it, and loads it into the register

Example of Loading and Storing Bytes Given following code sequence and memory state (contents are given in hexadecimal), what is the state of the memory after executing the code? add $s3, $zero, $zero lb $t0, 1($s3) sb $t0, 6($s3) Memory 0 0 0 0 0 0 0 0 24 What value is left in $t0? 0 0 0 0 0 0 0 0 20 0 0 0 0 0 0 0 0 16 For class handout What if the machine was little Endian? 1 0 0 0 0 0 1 0 12 0 1 0 0 0 4 0 2 8 F F F F F F F F 4 0 0 9 0 1 2 A 0 Data Word Address (Decimal)

MIPS Reference Data lb – load byte – loads a byte from memory, placing it in the rightmost 8 bits of a register. sb – store byte – takes a byte from the rightmost 8 bits of a register and writes it to memory

Example of Loading and Storing Bytes Given following code sequence and memory state (contents are given in hexadecimal), what is the state of the memory after executing the code? add $s3, $zero, $zero lb $t0, 1($s3) #lbu $t0, 1($s0)gives sb $t0, 6($s3) #$t0 = 0x00000090 mem(4) = 0xFFFF90FF Memory 0 0 0 0 0 0 0 0 24 Questions 2 : What value is left in $t0? 0 0 0 0 0 0 0 0 20 $t0 = 0xFFFFFF90 0 0 0 0 0 0 0 0 16 For lecture Big Endian Little Endian 0 1 2 3 3 2 1 0 $t0 gets 90 $t0 gets 12 word 4 gets FFFF90FF word 4 gets FF12FFFF 1 0 0 0 0 0 1 0 12 Questions 3: What if the machine was little Endian? 0 1 0 0 0 4 0 2 8 F F F F F F F F 4 mem(4) = 0xFF12FFFF $t0 = 0x00000012 0 0 9 0 1 2 A 0 Data Word Address (Decimal) * Class Participation

Review: MIPS Instructions, so far Category Instr Op Code Example Meaning Arithmetic (R format) add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s3 subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3 Data transfer (I format) load word 35 lw $s1, 100($s2) $s1 = Memory($s2+100) store word 43 sw $s1, 100($s2) Memory($s2+100) = $s1 load byte 32 lb $s1, 101($s2) $s1 = Memory($s2+101) store byte 40 sb $s1, 101($s2) Memory($s2+101) = $s1 similarity of the binary representation of related instructions simplifies the hardware design

Review: MIPS R3000 ISA Instruction Categories Load/Store Computational Jump and Branch Floating Point coprocessor Memory Management Special 3 Instruction Formats: all 32 bits wide Registers R0 - R31 PC HI LO 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R format OP rs rt rd shamt funct I format OP rs rt 16 bit number J format OP 26 bit jump target

Register Instructions Assume: g, h, i, j are stored in registers $s1 - $s4. Result f to be stored in $s0. Compile: f = (g + h) – (i + j) into MIPS instructions: add $t0, $s1, $s2 # register $t0  (g+h) add $t1, $s3, $s4 # $t1  (i + j) sub $s0, $t0, $t1 # $s0  $t0 - $t1 OP rs rt rd shft funct R-type

Immediate format Immediate = small constant stored in the instruction addi $sp, $sp, const # $sp  $sp + const OP const I-type 16 5 6 rt rs Range of constant operand: -215 ≤ const  215-1 Set on less-then, immediate slti $t0, $s2, const # $t0  1 if $s2 < const ; 0 otherwise

Operand in memory Let A[ ] = array whose starting (base) address is in $s3; let variable h be associated with register $s2; Compile: A[5] = h + A[8] into MIPS instructions: lw $t0, 32 ($s3) # $t0  A[8] add $t0, $s2, $t0 # $t0  h+$t0 sw $t0, 20 ($s3) # A[5]  $t0 8*4 = 32 bytes (byte-addressable) 8 7 6 5 4 3 2 1 $s3 5*4 = 20 OP rs rt immediate I-type

Array with variable index A[ ] = array with base address in $s3; variables g, h, i associated with registers $s1, $s2, $s4 Compile: g = h + A[i] into MIPS instructions: add $t1, $s4, $s4 # $t1  i+i = 2i add $t1, $t1, $t1 # $t1  2i+2i = 4i add $t1, $t1, $s3 # $t1  address of A[i] lw $t0, 0 ($t1) # $t0  A[i] add $s1, $s2, $t0 # $s1  h + A[i]

If statements Let variables f, g, h, i, j be associated with $s0 - $s4 Compile: if (i == j) go to L1; f = g + h; L1: f = f – i; into MIPS instructions: Does the following code work? beq $s3, $s4, L1 # if i = j, go to L1 add $s0, $s1, $s2 # f = g + h (skipped if i=j) L1: sub $s0, $s0, $s3 # f = f – i (always executed)

Jump instructions Regular jump uses J-format j Label # jump to Label 26 OP Label = jump target J-type (the above label is not quite this simple) jr (jump on register address) uses R-format jr $t1 # jump to address given in $t1 OP rs funct R-type OP/funct = jr

If then else statements Let variables f, g, h, i, j be associated with $s0 - $s4 Compile: if (i == j) f = g + h; else f = g –h; into MIPS instructions: bne $s3, $s4, Else # if i  j, go to Else add $s0, $s1, $s2 # f = g + h (skipped if i  j) j Exit # go to Exit Else: sub $s0, $s1, $s2 # f = g – h (skipped if i = j) Exit: OP jump target J-type

Pseudo-instructions Let variables a, b be associated with $s0, $s1 Compile: if (a < b) go to L into MIPS instructions: slt $t0, $s0, $s1 # $t0  1 if $s0 < $s1 (a < b) bne $t0, $zero, L # if $t0  0, go to L We can create pseudo-instruction: blt $s0, $s1, L Special registers, useful in beq, bne, slt: $zero is a special register, holds 0 $at is another special register used in the blt pseudo-instruction It generates the above two instructions with $at replacing $t0

Branching further away -215 ≤ small constant offset  215-1 Consider a branch instruction beq $s0, $s1, L1 # branch to L1 if $s0 = $s1 OP rs rt immediate I-type 16 5 6 If the offset does not fit in the above range the compiler (or programmer) changes it to the following sequence to get a larger distance. bne $s0, $s1, L2 # branch to L2 if $s0 $s1 j Large # unconditional jump to “Large” L2: OP Large – jump target J-type 6 26

Loading large numbers Instruction lui: load upper immediate lui $t0, const # $t0[31:16]  const OP const I-type 16 5 6 rt 16 $to: const 31 15 0000 0000 0000 0000

MIPS Addressing Modes/Instruction Formats All instructions are 32-bit wide op rs rt rd register Register (direct) immed op rs rt Immediate Base+index immed op rs rt register + Memory PC-relative immed op rs rt PC Memory + Also there is pseudodirect addressing as is used by jump instructions

Operation Summary Support these simple instructions, since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and, shift, compare equal, compare not equal, branch, jump, call, return;

Additional MIPS Instructions As opposed to CISC – Complicated Instruction Set Architecture (ala the x86)

MIPS instructions, formats MIPS instructions: data transfers, arithmetic, logical Pseudo-instruction example: loading large constant MIPS register organization Implementing loops Implementing switch/case statement Procedures and subroutines Stacks and pointers Running a program Compiler, Assembler, Linker, Loader c$redential: b$ring a compute$r die photo wafe$r : This can be an hidden slide. I just want to use this to do my own planning. I have $rea$r$ranged Culle$r’s lectu$re slides slightly and add mo$re slides. This cove$rs eve$rything he cove$rs in his fi$rst lectu$re (and mo$re) but may We will save the fun pa$rt, “ Levels of O$rganization,” at the end (so student can stay awake): I will show the inte$rnal st$rictu$re of the SS10/20. Notes to Patte$rson: You may want to edit the slides in you$r section o$r add ext$ra slides to taylo$r you$r needs.

MIPS: Software conventions for registers R0 $zero constant 0 R1 $at reserved for assembler R2 $v0 value registers & R3 $v1 function results R4 $a0 arguments R5 $a1 R6 $a2 R7 $a3 R8 $t0 temporary: caller saves . . . (callee can clobber) R15 $t7 R16 $s0 callee saves . . . (caller can clobber) R23 $s7 R24 $t8 temporary (cont’d) R25 $t9 R26 $k0 reserved for OS kernel R27 $k1 R28 $gp pointer to global area R29 $sp Stack pointer R30 $fp Frame pointer R31 $ra return Address

MIPS data transfer instructions Instruction Comment sw 500($r4), $r3 Store word sh 502($r2), $r3 Store half sb 41($r3), $r2 Store byte lw $r1, 30($r2) Load word lh $r1, 40($r3) Load halfword lhu $r1, 40($r3) Load halfword unsigned lb $r1, 40($r3) Load byte lbu $r1, 40($r3) Load byte unsigned lui $r1, 40 Load Upper Immediate (16 bits shifted left by 16) 0000 … 0000 LUI $r5 $r5

Loading large numbers Pseudo-instruction li $t0, big: load 32-bit constant lui $t0, upper # $t0[31:16]  upper ori $t0, $t0, lower # $t0  ($t0 Or [0ext.lower]) upper 16 31 15 0000 0000 0000 0000 OR lower 0000 0000 0000 0000 $to: upper lower 32-bit constant

Loop with variable array index Compile the following loop, with A[ ] = array with base address in $s5; variables g, h, i, j associated with registers $s1, $s2, $s3, $s4. Loop: g = g + A[i]; i = i + j; if (i  h) go to Loop; MIPS instructions: Loop: add $t1, $s3, $s3 # $t1  i+i = 2i add $t1, $t1, $t1 # $t1  2i+2i = 4i add $t1, $t1, $s5 # $t1  address of A[i] lw $t0, 0 ($t1) # $t0  A[i] add $s1, $s1, $t0 # $s1  g + A[i] add $s3, $s3, $s4 # $s3  i + j bne $s3, $s2, Loop # if (i  h) go to Loop

While loop while (A[i] == k) i = i + j; into MIPS instructions: Base address of A[i] is in $s6; variables i, j, k are in $s3, $s4, $s5. Compile the following while loop while (A[i] == k) i = i + j; into MIPS instructions: Loop: add $t1, $s3, $s3 # $t1  i+i = 2i add $t1, $t1, $t1 # $t1  2i+2i = 4i add $t1, $t1, $s6 # $t1  address of A[i] lw $t0, 0 ($t1) # $t0  A[i] bne $t0, $s5, Exit # if (A[I]  k) go to Exit add $s3, $s3, $s4 # $s3  i + j j Loop # go to Loop Exit:

Switch/case statement Variables f - k are in $s0 - $s5. Register $t2 contains constant 4. Compile the following switch statement into MIPS instructions switch (k) { case 0: f = i + j; break; /* k=0 */ case 1: f = g + h; break; /* k=1 */ case 2: f = g - h; break; /* k=2 */ case 3: f = i - j; break; /* k=3 */ } Use the switch variable k to index the jump address table. First, test for k, if in correct range (0-3). slt $t3, $s5, $zero # test if k , 0 bne $t3, $zero, Exit # if k < 0, go to Exit slt $t3, $s5, $t2 # test if k < 4 beq $t3, $zero, Exit # if k  4, go to Exit

Switch statement, cont’d Access jump table T [ ] with addresses L0,L1,L2,L3: $t4 is address of T add $t1, $s5, $s5 # $t1  2k add $t1, $t1, $t1 # $t1  4k add $t1, $t1, $t4 # $t1  address of T [k] lw $t0, 0 ($t1) # $t0  T [k] (loads one of L0, L1, L2, L3) Use jump register instruction to jump via $t0 to the right address jr $t0 # jump based on register $t0 L0: add $s0, $s3, $s4 # k = 0, so f=$s0  i + j j Exit # go to Exit L1: add $s0, $s1, $s2 # k = 1, so f=$s0  g + h L2: sub $s0, $s1, $s2 # k = 2, so f=$s0  g + h L3: sub $s0, $s3, $s4 # k = 3, so f=$s0  i - j Exit:

Compiling a leaf procedure (not nested) int leaf_example (int g, int h, int i, int j) { int f; f = (g + h) – (i + j); return f; } Let parameter variables g, h, i, j, correspond to the argument registers $a0, $a1, $a2, $a3. Will use temp. registers $t0= (g + h) and $t1=(i + j). Function f will be stored in $s0. Steps: Save the old values of registers ($s0, $t0, $t1) on stack (push) Issue a jal sub_address instruction ($ra  ret_addr, j sub_address) Perform the computation for $t0, $t1, $s0 using argument registers Copy the value of f into a return value register $v0 Restore the old values of the saved registers from stack (pop) Finally, jump back to the calling routine, jr $ra (PC  return_address=PC+4)

Compiling a leaf procedure, cont’d Leaf_example: # label of the procedure Save the old values of registers ($s0, $t0, $t1) on stack (push) sub $sp, $sp, 12 # adjust stack to make room for 3 items sw $t1, 8 ($sp) # save reg $t1 on stack ……. # repeat for $t0, $s0 Perform the computation for $t0, $t1, $s0 using argument registers add $t0, $a0, $a1 # $t0  g + h add $t1, $a2, $a3 # $t1  i + j sub $s0, $t0, $t1 # $s0  (g + h) – (i + j) Copy the value of f into a return value register $v0 add $v0, $s0, $zero # returns f ($v0  $s0 + 0) Restore the old values of the saved registers from stack (pop) lw $s0, 0 ($sp) # restore reg. $s0 for the caller ……. # repeat for $t0, $t1 … add $sp, $sp, 12 # adjust the stack to delete 3 items Finally, jump back to the calling routine (PC  return address) jr $ra # PC  $ra