Lecture 8: Sequential Networks and Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Fall 2014 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1

2 Combinational CLK A BC D Sequential Networks 1.Components F-Fs 2.Specification 3.Implementation: Excitation Table S(t) X Y CLK RTL: Register-Transfer Level Description

3 Specification Combinational Logic –Truth Table –Boolean Expression –Logic Diagram (No feedback loops) Sequential Networks: State Diagram (Memory) –State Table and Excitation Table –Characteristic Expression –Logic Diagram (FFs and feedback loops)

4 Specification: Finite State Machine Input Output Relation State Diagram (Transition of States) State Table Excitation Table (Truth table of FF inputs) Boolean Expression Logic Diagram

Specification: Examples Transition from circuit to finite state machine representation –Netlist => State Table => State Diagram => Input Output Relation Example 1: a circuit with D Flip Flops Example 2: a circuit with other Flip Flops 5

6 Building Sequential Circuits and describing their behavior

What we will learn: 7 1.Given a sequential circuit, describe its behavior over time 2.Given the behavior of a sequential circuit, implement the circuit Sequential Circuit: Wall-E How does Wall-E behave?

What does it mean to describe the behavior of a sequential circuit 8 Specify how the output of the circuit changes as a function of inputs and the state of the circuit

State: What is it? Why do we need it? 9 Free running 2 bit Counter Symbol/ Circuit Behavior over time time CLK Q0Q0 Q1Q1 What is the expected output of the counter over time?

State: What is it ? Why do we need it? 10 Symbol/ Circuit Behavior over time time CLK 2 bit Counter PI Q: At time t 1, what information is needed to produce the output of the counter at the next rising edge of the clock (i.e t 2 )? A.All the outputs of the counter until t 1 B.The initial output of the counter at time t=0 C.The output of the counter at current time t 1 D.We cannot determine the output of the counter at t 2 prior to t 2 t1t1 t2t2

Finite State Machines: Describing circuit behavior over time 11 2 bit Counter Symbol/ Circuit Diagram that depicts behavior over time

State Diagrams: Describing circuit behavior over time 12 State diagram of the 2 bit counter S0S0 S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 PI Q: What information is not explicitly indicated in the state diagram? A.The input to the circuit B.The output of the circuit C.The time when state transitions occur D.The current state of the circuit. E.The next state of the circuit. Finite State Machine

Implementing the 2 bit counter 13 S0S0 S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 State Diagram State Table Q 1 (t)Q 0 (t)Q 1 (t+1)Q 0 (t+1) Current stateNext State S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 S0S0

Implementing the 2 bit counter 14 S0S0 S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 State Diagram State Table Q 1 (t)Q 0 (t)Q 1 (t+1)Q 0 (t+1) Current stateNext State S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 S0S0

Implementing the 2 bit counter 15 State Table Q 1 (t)Q 0 (t)Q 1 (t+1)Q 0 (t+1) PI Q: To obtain the outputs Q 0 (t+1) and Q 1 (t+1) from the inputs Q 1 (t) and Q 0 (t) we need to use: A.Combinational logic B.Some other logic

Implementing the 2 bit counter 16 State Table Q 1 (t)Q 0 (t)Q 1 (t+1)Q 0 (t+1) Q 0 (t) Q 1 (t) Q 0 (t+1) Q 1 (t+1) PI Q: What is wrong with the 2-bit counter implementation shown above A.The combinational circuit is incorrect B.The circuit state changes correctly but continuously rather than at the rising edge of the clock signal C.The output of the circuit is unreliable because inputs can get corrupted

Implementing the 2 bit counter 17 State Table Q 1 (t)Q 0 (t)Q 1 (t+1)Q 0 (t+1) We store the current state using D-flip flops so that: The inputs to the combinational circuit don’t change while the next output is being computed The transition to the next state only occurs at the rising edge of the clock Q 0 (t) Q 1 (t) D Q Q’ D Q CLK Implementation of 2-bit counter Q 0 (t+1) = Q 0 (t)’ Q 1 (t+1) = Q 0 (t) Q 1 (t)’ + Q 0 (t)’ Q 1 (t)

18 Generalized Model of Sequential Circuits S(t) X Y CLK

Modified 2 bit counter 19 Q 0 (t) Q 1 (t) D Q Q’ D Q CLK x(t) Q 0 (t) Q 1 (t) y(t)

Modified 2 bit counter 20 Q 0 (t) Q 1 (t) D Q Q’ D Q CLK x(t) Q 0 (t) Q 1 (t) y(t ) Characteristic Expression: y(t) = Q 0 (t+1) = Q 1 (t+1) =

Modified 2 bit counter 21 Q 0 (t) Q 1 (t) D Q Q’ D Q CLK x(t) Q 0 (t) Q 1 (t) y(t) y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)’ Q 0 (t)’ Q 1 (t+1) = D 1 (t) = x(t)’(Q 0 (t) ⊕ Q 1 (t))

22 State table PS input x=0 x=1 Q 1 (t) Q 0 (t) | (Q 1 (t+1) Q 0 (t+1), y(t)) Present State | Next State, Output S0S1S2S3S0S1S2S3 PS input x=0 x=1 Netlist  State Table  State Diagram  Input Output Relation State Assignment Characteristic Expression: y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)’ Q 0 (t)’ Q 1 (t+1) = D 1 (t) = x(t)’(Q 0 (t) ⊕ Q 1 (t))

23 State table PS input x=0 x=1 01, 0 00, 0 10, 0 00, 0 11, 0 00, 0 00, 1 Q 1 (t) Q 0 (t) | Q 1 (t+1) Q 0 (t+1), y(t) Present State | Next State, Output S0S1S2S3S0S1S2S3 PS input x=0 x=1 S 1, 0 S 0, 0 S 2, 0 S 0, 0 S 3, 0 S 0, 0 S 0, 1 Let: S 0 = 00 S 1 = 01 S 2 = 10 S 3 = 11 Remake the state table using symbols instead of binary code, e.g. ’00’ Netlist  State Table  State Diagram  Input Output Relation State Assignment y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)’ Q 0 (t)’ Q 1 (t+1) = D 1 (t) = x(t)’(Q 0 (t) + Q 1 (t))

24 Netlist  State Table  State Diagram  Input Output Relation Given inputs and initial state, derive output sequence S1S1 S2S2 S3S3 S0S0 Time Input StateS0 Output S0S1S2S3S0S1S2S3 PS input x=0 x=1 S 1, 0 S 0, 0 S 2, 0 S 0, 0 S 3, 0 S 0, 0 S 0, 1

25 Netlist  State Table  State Diagram  Input Output Relation Example: Given inputs and initial state, derive output sequence x/y S1S1 S2S2 S3S3 S0S0 0/0 1/0 Time Input StateS0S1S0S1S2S3 Output (0 or 1)/1 S0S1S2S3S0S1S2S3 PS input x=0 x=1 S 1, 0 S 0, 0 S 2, 0 S 0, 0 S 3, 0 S 0, 0 S 0, 1 1/0

26 Let’s implement our free running 2-bit counter using T-flip flops S0S1S2S3S0S1S2S3 PS Next state S1S2S3S0S1S2S3S0 State Table S0S0 S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3

27 Let’s implement our free running 2-bit counter using T-flip flops S0S1S2S3S0S1S2S3 S1S2S3S0S1S2S3S0 State Table S0S0 S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 State Table with Assigned Encoding Current Next

28 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) Excitation table

29 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) Excitation table

30 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) Excitation table T 0 (t) = T 1 (t) = Q 0 (t+1) = T 0 (t) Q’ 0 (t)+T’ 0 (t)Q 0 (t) Q 1 (t+1) = T 1 (t) Q’ 1 (t)+T’ 1 (t)Q 1 (t)

31 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) Excitation table T 0 (t) = 1 T 1 (t) = Q 0 (t)

32 T Q Q’ T Q Q0Q0 Q1Q1 1 T1T1 Free running counter with T flip flops T 0 (t) = 1 T 1 (t) = Q 0 (t)

33 y(t) = Q 1 (t)Q 0 (t) T 0 (t) = x(t) Q 1 (t) T 1 (t) = x(t) + Q 0 (t) X T Q Q’ T Q y Q0Q0 Q1Q1 T0T0 T1T1 Example 3 Circuit with T Flip-Flops

34 Logic Diagram => Excitation Table => State Table y(t) = Q 1 (t)Q 0 (t) T 0 (t) = x(t) Q 1 (t) T 1 (t) = x(t) + Q 0 (t) Q 0 (t+1) = T 0 (t) Q’ 0 (t)+T’ 0 (t)Q 0 (t) Q 1 (t+1) = T 1 (t) Q’ 1 (t)+T’ 1 (t)Q 1 (t) idQ 1 (t)Q 0 (t)xT 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1)y Excitation Table: Truth table of the F-F inputs

Excitation Table: iClicker 35 In excitation table, the inputs of the flip flops are used to produce A.The present state B.The next state

36 idQ 1 (t)Q 0 (t)xT 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1)y Excitation Table =>State Table => State Diagram PS\InputX=0X=1 S0 S1 S2 S3 State Assignment S0 00 S1 01 S2 10 S3 11

37 idQ 1 (t)Q 0 (t)xT 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1)y Excitation Table =>State Table => State Diagram S0 S1S3 S2 PS\InputX=0X=1 S0S0,0S2,0 S1S3,0 S2S2,0S1,0 S3S1,1S0,1 State Assignment S0 00 S1 01 S2 10 S3 11

38 idQ 1 (t)Q 0 (t)xT 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1)y Excitation Table =>State Table => State Diagram 0/0 S0 S1S3 S2 0/0 1/1 0/1 0, 1/01/0 PS\InputX=0X=1 S0S0,0S2,0 S1S3,0 S2S2,0S1,0 S3S1,1S0,1 State Assignment S0 00 S1 01 S2 10 S3 11

39 Netlist  State Table  State Diagram  Input Output Relation 0/0 S0 S1S3 S2 0/0 1/1 0/1 0, 1/01/0 PS\InputX=0X=1 S0S0,0S2,0 S1S3,0 S2S2,0S1,0 S3S1,0S0,1 Time Input StateS0 Output Example: Output sequence

40 Netlist  State Table  State Diagram  Input Output Relation 0/0 S0 S1S3 S2 0/0 1/1 0/1 0, 1/01/0 PS\InputX=0X=1 S0S0,0S2,0 S1S3,0 S2S2,0S1,0 S3S1,0S0,1 Time Input StateS0 S2S1S3S0 Output Example: Output sequence

Implementation 41 State Diagram => State Table => Logic Diagram Canonical Form: Mealy and Moore Machines Excitation Table Truth Table of the F-F Inputs Boolean algebra, K-maps for combinational logic Examples Timing

42 Canonical Form: Mealy and Moore Machines Combinational Logic x(t) y(t) CLK C2 C1 y(t) CLK x(t) C1C2 CLK x(t) y(t)

43 Mealy Machine: y i (t) = f i (X(t), S(t)) Moore Machine: y i (t) = f i (S(t)) s i (t+1) = g i (X(t), S(t)) C1C2 CLK x(t) y(t) Mealy Machine C1C2 CLK x(t) y(t) Moore Machine S(t) Canonical Form: Mealy and Moore Machines

44 Implementation: State Diagram => State Table => Netlist Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0. Assign mapping a:0, b:1

45 Implementation: State Diagram => State Table => Netlist Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0. Assign mapping a:0, b:1 PI Q How many states should the pattern recognizer have A.One because it has one output B.One because it has one input C.Two because the input can be one of two states (a or b) D.Three because E.Four because.....

46 PI Q: How many states should the pattern recognizer have A.One because it has one output B.One because it has one input C.Two because the input can be one of two states (a or b) D.Three because E.Four because.....

47 Implementation: State Diagram => State Table => Netlist Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0. S1 S0 a/0 b/0 a/0 b/1 S2 a/0 b/0

48 State Diagram => State Table with State Assignment State Assignment S0: 00 S1: 01 S2: 10 PS\xab S0S1,0S0,0 S1S2,0S0,0 S2S2,0S0,1 PS\x ,000,0 0110,000,0 1010,000,1 Q 1 (t+1)Q 0 (t+1), y a: 0 b: 1 S1 S0 a/0 b/0 a/0 b/1 S2 a/0 b/0

49 Example 2: State Diagram => State Table => Excitation Table => Netlist PS\x ,000,0 0110,000,0 1010,000,1 idQ1Q0xQ1Q0xD1D0D1D0 y

x(t) Q1Q Q0Q0 D 1 (t): D 1 (t) = x’Q 0 + x’Q 1 D 0 (t)= Q’ 1 Q’ 0 x’ y= Q 1 x idQ1Q0xQ1Q0xD1D0D1D0 y Example 2: State Diagram => State Table => Excitation Table => Netlist

51 D Q Q’ D Q Q1Q1 Q0Q0 D1D1 D0D0 Q0Q0 Q1Q1 x’ D 1 (t) = x’Q 0 + x’Q 1 D 0 (t)= Q’ 1 Q’ 0 x’ y= Q 1 x x y Q’ 1 Q’ 0 x’ Example 2: State Diagram => State Table => Excitation Table => Netlist

52 D Q Q’ D Q Q1Q1 Q0Q0 D1D1 D0D0 Q0Q0 Q1Q1 x’ x y Q’ 1 Q’ 0 x’ Example 3: State Diagram => State Table => Excitation Table => Netlist S1 S0 a/0 b/0 a/0 b/1 S2 a/0 b/0 iClicker: The relation between the above state diagram and sequential circuit. A.One to one. B.One to many C.Many to one D.Many to many E.None of the above

53 Finite State Machine Example Traffic light controller –Traffic sensors: T A, T B (TRUE when there’s traffic) –Lights: L A, L B

54 FSM Black Box Inputs: CLK, Reset, T A, T B Outputs: L A, L B

55 FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs

56 FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs

57 FSM State Transition Table PSInputsNS TATA TBTB S00XS1 S01X S1XXS2 X0S3 S2X1 S3XXS0

58 State Transition Table PSInputsNS Q 1 (t)Q 0 (t)TATA TBTB Q 1 (t +1)Q 0 (t +1) 000X01 001X00 01XX10 10X011 10X110 11XX00 StateEncoding S000 S101 S210 S311 Q 1 (t+1)= Q 1 (t)  Q 0 (t) Q 0 (t+1)= Q’ 1 (t)Q’ 0 (t)T’ A + Q 1 (t)Q’ 0 (t)T’ B

59 FSM Output Table PSOutputs Q1Q1 Q0Q0 LA1LA1 LA0LA0 LB1LB1 LB0LB OutputEncoding green00 yellow01 red10 L A1 = Q 1 L A0 = Q’ 1 Q 0 L B1 = Q’ 1 L B0 = Q 1 Q 0

60 FSM Schematic: State Register

61 Logic Diagram

62 FSM Schematic: Output Logic