Designing Synchronization Sources in a Network Element Dejan Habic Raltron Electronics Corp.

Agenda zA generic timing system solution in NE zClock cards architecture zLine cards synchronization sources zPerformance Evaluation and test results examples

HF PLL Line Card 2 Framer (OCx) PLL Line Card n+1 Framer (DSx) A Generic Timing Solution in NE Input Clock System Clock Card 2 Host  P Input Clock System Clock Card 1 Host  P DS1,E1, Bits In HF PLL Line Card 1 Framer (OCx) PLL Line Card n Framer (DSx) Back plane

zFunctionality zPerformance zRedundancy or overall robustness of the system. zAutomatic respond to all external or internal events at all levels. zAlarm and status signal messages. zControl interface to the all elements of the system. A Generic Timing Solution – attributes

zNumber of external reference inputs zNumber of output signals required zSelecting the local oscillator (LO) for required quality of the clock zFiltering algorithms zReference qualification zPhase transient suppression zHoldover performance zSwitching between the modes zMaster-slave operation of the two clocks Clock Card Architecture - general issues

Phase Detector & MUX VCXODAC Loop Filter & Control t Clock Architecture – SPLL type 1

zSupports all modes of operation (locked, holdover and free-run) zLoop parameters can be optimized in software and changed dynamically during operation zEasy to achieve low bandwidth PLL zEasy to change in software for different requirements (timing; switching) zTemperature and other stability compensation of the LO can be implemented. zDigital noise in the loop zHigh-pull VCXO and DAC are issues to consider. Clock Architecture – SPLL type 1

T,U,... Phase Detector & MUX Free Running Oscillator DDS Loop Filter & Control Output Synthesizer Clock Architecture – SPLL type 2

zSupports all modes of operation (locked, holdover and free run) zEasier to achieve higher accuracy of the clock (e.g. Stratum 3E). zOscillator is free running reference zEasier to control the loop zLoop parameters can be optimized in software and changed dynamically zEasy to achieve low bandwidth zEasy to change in software for different requirements (timing; switching) zVarious disciplining algorithms for control of the LO can be implemented. zDigital noise in the loop zPhase noise and spurious due to DDS should be carefully considered. Clock Architecture – SPLL type 2

Line Cards Timing – General Issues zGenerate highest possible frequency required by system with the cleanest output signal – crystal or SAW based oscillators. zThe output oscillator should be with very good jitter performance – avoid signal multiplication if possible, using high frequency fundamental crystal technologies zThe PLL should be optimized with respect to in/output frequencies, possible transients during switching etc… zShould provide smooth switching between two references. zShould provide control interface, statuses and alarm messages.

MUX & Control VCXOPLL Line Cards Timing – Switching + PLL Reference 1 Reference 2 To Framer Statuses, Alarms and Control

zSimple analog implementation of PLL with low jitter frequency source at the output. zProvide automatic switching between two references. zPossible to implement a “hit-less” switching. zInterface for status, control and monitoring. zDifferent frequency sources require new optimizations of the loop. zInfluence of temperature, aging and other environmental effects on the frequency source should be considered. Line Cards Timing – Switching + PLL

Characterizing the behavior of the system zParameters and behavior are well defined and specified by international recommendations (BellCore, ANSI, ITU-T, ETSI). zImportant to ensure that the system complies with the recommendations. zProve system performance.

Measurement and Analysis zDetermine measurement equipment zDetermine set up of the equipment for specific measurements zFollow the measurement procedures zMeasurements zAnalysis and interpreting the results

The types of measurements zFrequency accuracy – (ppm) zPull-in, Hold-in… – (ppm) zJitter and wander generation (TIE, MTIE, TDEV) zWander tolerance – (TIE, MTIE, TDEV) zHoldover performance – (TIE, MTIE, f(T,t)…) zSwitching and transient – (TIE, MTIE) zOther tests such as environmental tests…

Measurement – wander generation zWander generation – the amount of noise produced at the output when an ideal input is applied. zSignal with white noise applied at the input. zMeasured TIE for a given observation time period z Calculate MTIE and TDEV

zWander tolerance – the tolerable level of noise at the input, while keeping the output within the recommended limits. zsignal with known/specified noise distribution applied at the input zMeasure TIE for a given observation time period zCalculation of TDEV zThe system should operate without any alarm, switch reference or to holdover mode. Measurement – wander tolerance

zBehavior of the output during reference switching - output phase transient. zThe unit is locked to one reference and then switched to another one. zMeasure TIE during that period zCalculate MTIE Measurement – reference switching

 The response of the output phase when a 1  s phase transient is applied at the input. zThe unit is locked to the reference when the transient is generated. zMeasure TIE during the event. zCalculate MTIE. zEvaluate PLL parameters - damping factor, peaking… Measurement – 1  s transient

zThe response quite different when phase build-out feature is implemented. Measurement – 1  s transient with phase build-out implemented

zThe whole set of test that characterize holdover operation. zInitial frequency offset. zThe frequency offset due to temperature changes. zThe frequency offset due to aging. zThe additional frequency offset. Measurement – holdover performance

zParameters’ testing over extreme environmental conditions (e.g. wander generation as a function of temperature). zTIE measurement while exposing the DUT to temperature variations. zExternal variations of environmental conditions may effect power supply stability, performance under vibrations, humidity, etc… Measurement – environment testing

Summary zUnderstand all the requirements of synchronization for a particular product. zDetermine specifications and performances to be achieved. zDetermine the role of each element in the system and integration impact amongst them. zSelect and evaluate each components in the system. zIntegrate a system. zTest and characterize it.